astyle --formatted --mode=c --indent=spaces=2 --indent-switches --indent-preprocessor --keep-one-line-blocks --max-instatement-indent=60 --brackets=linux --pad-oper --unpad-paren --pad-header
This commit is contained in:
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59 changed files with 3178 additions and 3178 deletions
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@ -144,49 +144,49 @@ typedef enum {
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static const pn53x_command pn53x_commands[] = {
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// Miscellaneous
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PNCMD( Diagnose, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( GetFirmwareVersion, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( GetGeneralStatus, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( ReadRegister, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( WriteRegister, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( ReadGPIO, PN531 | PN532 | PN533 ),
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PNCMD( WriteGPIO, PN531 | PN532 | PN533 ),
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PNCMD( SetSerialBaudRate, PN531 | PN532 | PN533 ),
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PNCMD( SetParameters, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( SAMConfiguration, PN531 | PN532 ),
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PNCMD( PowerDown, PN531 | PN532 ),
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PNCMD( AlparCommandForTDA, PN533 | RCS360 ), // Has another usage on RC-S360...
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PNCMD(Diagnose, PN531 | PN532 | PN533 | RCS360),
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PNCMD(GetFirmwareVersion, PN531 | PN532 | PN533 | RCS360),
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PNCMD(GetGeneralStatus, PN531 | PN532 | PN533 | RCS360),
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PNCMD(ReadRegister, PN531 | PN532 | PN533 | RCS360),
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PNCMD(WriteRegister, PN531 | PN532 | PN533 | RCS360),
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PNCMD(ReadGPIO, PN531 | PN532 | PN533),
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PNCMD(WriteGPIO, PN531 | PN532 | PN533),
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PNCMD(SetSerialBaudRate, PN531 | PN532 | PN533),
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PNCMD(SetParameters, PN531 | PN532 | PN533 | RCS360),
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PNCMD(SAMConfiguration, PN531 | PN532),
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PNCMD(PowerDown, PN531 | PN532),
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PNCMD(AlparCommandForTDA, PN533 | RCS360), // Has another usage on RC-S360...
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// RF communication
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PNCMD( RFConfiguration, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( RFRegulationTest, PN531 | PN532 | PN533 ),
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PNCMD(RFConfiguration, PN531 | PN532 | PN533 | RCS360),
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PNCMD(RFRegulationTest, PN531 | PN532 | PN533),
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// Initiator
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PNCMD( InJumpForDEP, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( InJumpForPSL, PN531 | PN532 | PN533 ),
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PNCMD( InListPassiveTarget, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( InATR, PN531 | PN532 | PN533 ),
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PNCMD( InPSL, PN531 | PN532 | PN533 ),
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PNCMD( InDataExchange, PN531 | PN532 | PN533 ),
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PNCMD( InCommunicateThru, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( InQuartetByteExchange, PN533 ),
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PNCMD( InDeselect, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( InRelease, PN531 | PN532 | PN533 | RCS360 ),
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PNCMD( InSelect, PN531 | PN532 | PN533 ),
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PNCMD( InAutoPoll, PN532 ),
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PNCMD( InActivateDeactivatePaypass, PN533 ),
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PNCMD(InJumpForDEP, PN531 | PN532 | PN533 | RCS360),
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PNCMD(InJumpForPSL, PN531 | PN532 | PN533),
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PNCMD(InListPassiveTarget, PN531 | PN532 | PN533 | RCS360),
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PNCMD(InATR, PN531 | PN532 | PN533),
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PNCMD(InPSL, PN531 | PN532 | PN533),
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PNCMD(InDataExchange, PN531 | PN532 | PN533),
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PNCMD(InCommunicateThru, PN531 | PN532 | PN533 | RCS360),
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PNCMD(InQuartetByteExchange, PN533),
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PNCMD(InDeselect, PN531 | PN532 | PN533 | RCS360),
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PNCMD(InRelease, PN531 | PN532 | PN533 | RCS360),
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PNCMD(InSelect, PN531 | PN532 | PN533),
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PNCMD(InAutoPoll, PN532),
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PNCMD(InActivateDeactivatePaypass, PN533),
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// Target
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PNCMD( TgInitAsTarget, PN531 | PN532 | PN533 ),
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PNCMD( TgSetGeneralBytes, PN531 | PN532 | PN533 ),
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PNCMD( TgGetData, PN531 | PN532 | PN533 ),
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PNCMD( TgSetData, PN531 | PN532 | PN533 ),
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PNCMD( TgSetDataSecure, PN533 ),
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PNCMD( TgSetMetaData, PN531 | PN532 | PN533 ),
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PNCMD( TgSetMetaDataSecure, PN533 ),
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PNCMD( TgGetInitiatorCommand, PN531 | PN532 | PN533 ),
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PNCMD( TgResponseToInitiator, PN531 | PN532 | PN533 ),
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PNCMD( TgGetTargetStatus, PN531 | PN532 | PN533 ),
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PNCMD(TgInitAsTarget, PN531 | PN532 | PN533),
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PNCMD(TgSetGeneralBytes, PN531 | PN532 | PN533),
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PNCMD(TgGetData, PN531 | PN532 | PN533),
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PNCMD(TgSetData, PN531 | PN532 | PN533),
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PNCMD(TgSetDataSecure, PN533),
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PNCMD(TgSetMetaData, PN531 | PN532 | PN533),
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PNCMD(TgSetMetaDataSecure, PN533),
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PNCMD(TgGetInitiatorCommand, PN531 | PN532 | PN533),
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PNCMD(TgResponseToInitiator, PN531 | PN532 | PN533),
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PNCMD(TgGetTargetStatus, PN531 | PN532 | PN533),
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};
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// SFR part
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@ -330,76 +330,76 @@ typedef struct {
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#ifdef LOGGING
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static const pn53x_register pn53x_registers[] = {
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PNREG (PN53X_REG_CIU_Mode, "Defines general modes for transmitting and receiving"),
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PNREG (PN53X_REG_CIU_TxMode, "Defines the transmission data rate and framing during transmission"),
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PNREG (PN53X_REG_CIU_RxMode, "Defines the transmission data rate and framing during receiving"),
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PNREG (PN53X_REG_CIU_TxControl, "Controls the logical behaviour of the antenna driver pins TX1 and TX2"),
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PNREG (PN53X_REG_CIU_TxAuto, "Controls the settings of the antenna driver"),
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PNREG (PN53X_REG_CIU_TxSel, "Selects the internal sources for the antenna driver"),
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PNREG (PN53X_REG_CIU_RxSel, "Selects internal receiver settings"),
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PNREG (PN53X_REG_CIU_RxThreshold, "Selects thresholds for the bit decoder"),
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PNREG (PN53X_REG_CIU_Demod, "Defines demodulator settings"),
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PNREG (PN53X_REG_CIU_FelNFC1, "Defines the length of the valid range for the received frame"),
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PNREG (PN53X_REG_CIU_FelNFC2, "Defines the length of the valid range for the received frame"),
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PNREG (PN53X_REG_CIU_MifNFC, "Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit/s"),
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PNREG (PN53X_REG_CIU_ManualRCV, "Allows manual fine tuning of the internal receiver"),
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PNREG (PN53X_REG_CIU_TypeB, "Configure the ISO/IEC 14443 type B"),
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PNREG(PN53X_REG_CIU_Mode, "Defines general modes for transmitting and receiving"),
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PNREG(PN53X_REG_CIU_TxMode, "Defines the transmission data rate and framing during transmission"),
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PNREG(PN53X_REG_CIU_RxMode, "Defines the transmission data rate and framing during receiving"),
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PNREG(PN53X_REG_CIU_TxControl, "Controls the logical behaviour of the antenna driver pins TX1 and TX2"),
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PNREG(PN53X_REG_CIU_TxAuto, "Controls the settings of the antenna driver"),
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PNREG(PN53X_REG_CIU_TxSel, "Selects the internal sources for the antenna driver"),
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PNREG(PN53X_REG_CIU_RxSel, "Selects internal receiver settings"),
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PNREG(PN53X_REG_CIU_RxThreshold, "Selects thresholds for the bit decoder"),
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PNREG(PN53X_REG_CIU_Demod, "Defines demodulator settings"),
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PNREG(PN53X_REG_CIU_FelNFC1, "Defines the length of the valid range for the received frame"),
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PNREG(PN53X_REG_CIU_FelNFC2, "Defines the length of the valid range for the received frame"),
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PNREG(PN53X_REG_CIU_MifNFC, "Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit/s"),
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PNREG(PN53X_REG_CIU_ManualRCV, "Allows manual fine tuning of the internal receiver"),
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PNREG(PN53X_REG_CIU_TypeB, "Configure the ISO/IEC 14443 type B"),
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// PNREG (PN53X_REG_-, "Reserved"),
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// PNREG (PN53X_REG_-, "Reserved"),
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PNREG (PN53X_REG_CIU_CRCResultMSB, "Shows the actual MSB values of the CRC calculation"),
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PNREG (PN53X_REG_CIU_CRCResultLSB, "Shows the actual LSB values of the CRC calculation"),
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PNREG (PN53X_REG_CIU_GsNOFF, "Selects the conductance of the antenna driver pins TX1 and TX2 for load modulation when own RF field is switched OFF"),
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PNREG (PN53X_REG_CIU_ModWidth, "Controls the setting of the width of the Miller pause"),
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PNREG (PN53X_REG_CIU_TxBitPhase, "Bit synchronization at 106 kbit/s"),
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PNREG (PN53X_REG_CIU_RFCfg, "Configures the receiver gain and RF level"),
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PNREG (PN53X_REG_CIU_GsNOn, "Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when own RF field is switched ON"),
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PNREG (PN53X_REG_CIU_CWGsP, "Selects the conductance of the antenna driver pins TX1 and TX2 when not in modulation phase"),
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PNREG (PN53X_REG_CIU_ModGsP, "Selects the conductance of the antenna driver pins TX1 and TX2 when in modulation phase"),
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PNREG (PN53X_REG_CIU_TMode, "Defines settings for the internal timer"),
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PNREG (PN53X_REG_CIU_TPrescaler, "Defines settings for the internal timer"),
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PNREG (PN53X_REG_CIU_TReloadVal_hi, "Describes the 16-bit long timer reload value (Higher 8 bits)"),
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PNREG (PN53X_REG_CIU_TReloadVal_lo, "Describes the 16-bit long timer reload value (Lower 8 bits)"),
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PNREG (PN53X_REG_CIU_TCounterVal_hi, "Describes the 16-bit long timer actual value (Higher 8 bits)"),
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PNREG (PN53X_REG_CIU_TCounterVal_lo, "Describes the 16-bit long timer actual value (Lower 8 bits)"),
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PNREG(PN53X_REG_CIU_CRCResultMSB, "Shows the actual MSB values of the CRC calculation"),
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PNREG(PN53X_REG_CIU_CRCResultLSB, "Shows the actual LSB values of the CRC calculation"),
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PNREG(PN53X_REG_CIU_GsNOFF, "Selects the conductance of the antenna driver pins TX1 and TX2 for load modulation when own RF field is switched OFF"),
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PNREG(PN53X_REG_CIU_ModWidth, "Controls the setting of the width of the Miller pause"),
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PNREG(PN53X_REG_CIU_TxBitPhase, "Bit synchronization at 106 kbit/s"),
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PNREG(PN53X_REG_CIU_RFCfg, "Configures the receiver gain and RF level"),
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PNREG(PN53X_REG_CIU_GsNOn, "Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when own RF field is switched ON"),
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PNREG(PN53X_REG_CIU_CWGsP, "Selects the conductance of the antenna driver pins TX1 and TX2 when not in modulation phase"),
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PNREG(PN53X_REG_CIU_ModGsP, "Selects the conductance of the antenna driver pins TX1 and TX2 when in modulation phase"),
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PNREG(PN53X_REG_CIU_TMode, "Defines settings for the internal timer"),
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PNREG(PN53X_REG_CIU_TPrescaler, "Defines settings for the internal timer"),
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PNREG(PN53X_REG_CIU_TReloadVal_hi, "Describes the 16-bit long timer reload value (Higher 8 bits)"),
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PNREG(PN53X_REG_CIU_TReloadVal_lo, "Describes the 16-bit long timer reload value (Lower 8 bits)"),
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PNREG(PN53X_REG_CIU_TCounterVal_hi, "Describes the 16-bit long timer actual value (Higher 8 bits)"),
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PNREG(PN53X_REG_CIU_TCounterVal_lo, "Describes the 16-bit long timer actual value (Lower 8 bits)"),
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// PNREG (PN53X_REG_-, "Reserved"),
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PNREG (PN53X_REG_CIU_TestSel1, "General test signals configuration"),
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PNREG (PN53X_REG_CIU_TestSel2, "General test signals configuration and PRBS control"),
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PNREG (PN53X_REG_CIU_TestPinEn, "Enables test signals output on pins."),
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PNREG (PN53X_REG_CIU_TestPinValue, "Defines the values for the 8-bit parallel bus when it is used as I/O bus"),
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PNREG (PN53X_REG_CIU_TestBus, "Shows the status of the internal test bus"),
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PNREG (PN53X_REG_CIU_AutoTest, "Controls the digital self-test"),
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PNREG (PN53X_REG_CIU_Version, "Shows the CIU version"),
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PNREG (PN53X_REG_CIU_AnalogTest, "Controls the pins AUX1 and AUX2"),
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PNREG (PN53X_REG_CIU_TestDAC1, "Defines the test value for the TestDAC1"),
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PNREG (PN53X_REG_CIU_TestDAC2, "Defines the test value for the TestDAC2"),
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PNREG (PN53X_REG_CIU_TestADC, "Show the actual value of ADC I and Q"),
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PNREG(PN53X_REG_CIU_TestSel1, "General test signals configuration"),
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PNREG(PN53X_REG_CIU_TestSel2, "General test signals configuration and PRBS control"),
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PNREG(PN53X_REG_CIU_TestPinEn, "Enables test signals output on pins."),
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PNREG(PN53X_REG_CIU_TestPinValue, "Defines the values for the 8-bit parallel bus when it is used as I/O bus"),
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PNREG(PN53X_REG_CIU_TestBus, "Shows the status of the internal test bus"),
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PNREG(PN53X_REG_CIU_AutoTest, "Controls the digital self-test"),
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PNREG(PN53X_REG_CIU_Version, "Shows the CIU version"),
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PNREG(PN53X_REG_CIU_AnalogTest, "Controls the pins AUX1 and AUX2"),
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PNREG(PN53X_REG_CIU_TestDAC1, "Defines the test value for the TestDAC1"),
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PNREG(PN53X_REG_CIU_TestDAC2, "Defines the test value for the TestDAC2"),
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PNREG(PN53X_REG_CIU_TestADC, "Show the actual value of ADC I and Q"),
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// PNREG (PN53X_REG_-, "Reserved for tests"),
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// PNREG (PN53X_REG_-, "Reserved for tests"),
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// PNREG (PN53X_REG_-, "Reserved for tests"),
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PNREG (PN53X_REG_CIU_RFlevelDet, "Power down of the RF level detector"),
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PNREG (PN53X_REG_CIU_SIC_CLK_en, "Enables the use of secure IC clock on P34 / SIC_CLK"),
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PNREG (PN53X_REG_CIU_Command, "Starts and stops the command execution"),
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PNREG (PN53X_REG_CIU_CommIEn, "Control bits to enable and disable the passing of interrupt requests"),
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PNREG (PN53X_REG_CIU_DivIEn, "Controls bits to enable and disable the passing of interrupt requests"),
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PNREG (PN53X_REG_CIU_CommIrq, "Contains common CIU interrupt request flags"),
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PNREG (PN53X_REG_CIU_DivIrq, "Contains miscellaneous interrupt request flags"),
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PNREG (PN53X_REG_CIU_Error, "Error flags showing the error status of the last command executed"),
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PNREG (PN53X_REG_CIU_Status1, "Contains status flags of the CRC, Interrupt Request System and FIFO buffer"),
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PNREG (PN53X_REG_CIU_Status2, "Contain status flags of the receiver, transmitter and Data Mode Detector"),
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PNREG (PN53X_REG_CIU_FIFOData, "In- and output of 64 byte FIFO buffer"),
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PNREG (PN53X_REG_CIU_FIFOLevel, "Indicates the number of bytes stored in the FIFO"),
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PNREG (PN53X_REG_CIU_WaterLevel, "Defines the thresholds for FIFO under- and overflow warning"),
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PNREG (PN53X_REG_CIU_Control, "Contains miscellaneous control bits"),
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PNREG (PN53X_REG_CIU_BitFraming, "Adjustments for bit oriented frames"),
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PNREG (PN53X_REG_CIU_Coll, "Defines the first bit collision detected on the RF interface"),
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PNREG(PN53X_REG_CIU_RFlevelDet, "Power down of the RF level detector"),
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PNREG(PN53X_REG_CIU_SIC_CLK_en, "Enables the use of secure IC clock on P34 / SIC_CLK"),
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PNREG(PN53X_REG_CIU_Command, "Starts and stops the command execution"),
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PNREG(PN53X_REG_CIU_CommIEn, "Control bits to enable and disable the passing of interrupt requests"),
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PNREG(PN53X_REG_CIU_DivIEn, "Controls bits to enable and disable the passing of interrupt requests"),
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PNREG(PN53X_REG_CIU_CommIrq, "Contains common CIU interrupt request flags"),
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PNREG(PN53X_REG_CIU_DivIrq, "Contains miscellaneous interrupt request flags"),
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PNREG(PN53X_REG_CIU_Error, "Error flags showing the error status of the last command executed"),
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PNREG(PN53X_REG_CIU_Status1, "Contains status flags of the CRC, Interrupt Request System and FIFO buffer"),
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PNREG(PN53X_REG_CIU_Status2, "Contain status flags of the receiver, transmitter and Data Mode Detector"),
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PNREG(PN53X_REG_CIU_FIFOData, "In- and output of 64 byte FIFO buffer"),
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PNREG(PN53X_REG_CIU_FIFOLevel, "Indicates the number of bytes stored in the FIFO"),
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PNREG(PN53X_REG_CIU_WaterLevel, "Defines the thresholds for FIFO under- and overflow warning"),
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PNREG(PN53X_REG_CIU_Control, "Contains miscellaneous control bits"),
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PNREG(PN53X_REG_CIU_BitFraming, "Adjustments for bit oriented frames"),
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PNREG(PN53X_REG_CIU_Coll, "Defines the first bit collision detected on the RF interface"),
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// SFR
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PNREG (PN53X_SFR_P3CFGA, "Port 3 configuration"),
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PNREG (PN53X_SFR_P3CFGB, "Port 3 configuration"),
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PNREG (PN53X_SFR_P3, "Port 3 value"),
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PNREG (PN53X_SFR_P7CFGA, "Port 7 configuration"),
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PNREG (PN53X_SFR_P7CFGB, "Port 7 configuration"),
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PNREG (PN53X_SFR_P7, "Port 7 value"),
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PNREG(PN53X_SFR_P3CFGA, "Port 3 configuration"),
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PNREG(PN53X_SFR_P3CFGB, "Port 3 configuration"),
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PNREG(PN53X_SFR_P3, "Port 3 value"),
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PNREG(PN53X_SFR_P7CFGA, "Port 7 configuration"),
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PNREG(PN53X_SFR_P7CFGB, "Port 7 configuration"),
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PNREG(PN53X_SFR_P7, "Port 7 value"),
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};
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#endif
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File diff suppressed because it is too large
Load diff
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@ -292,102 +292,102 @@ extern const uint8_t pn53x_ack_frame[6];
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extern const uint8_t pn53x_nack_frame[6];
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int pn53x_init(struct nfc_device *pnd);
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int pn53x_transceive (struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx, uint8_t *pbtRx, const size_t szRxLen, int timeout);
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int pn53x_transceive(struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx, uint8_t *pbtRx, const size_t szRxLen, int timeout);
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int pn53x_set_parameters (struct nfc_device *pnd, const uint8_t ui8Value, const bool bEnable);
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int pn53x_set_tx_bits (struct nfc_device *pnd, const uint8_t ui8Bits);
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int pn53x_wrap_frame (const uint8_t *pbtTx, const size_t szTxBits, const uint8_t *pbtTxPar, uint8_t *pbtFrame);
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int pn53x_unwrap_frame (const uint8_t *pbtFrame, const size_t szFrameBits, uint8_t *pbtRx, uint8_t *pbtRxPar);
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int pn53x_decode_target_data (const uint8_t *pbtRawData, size_t szRawData,
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pn53x_type chip_type, nfc_modulation_type nmt,
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nfc_target_info *pnti);
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int pn53x_read_register (struct nfc_device *pnd, uint16_t ui16Reg, uint8_t *ui8Value);
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int pn53x_write_register (struct nfc_device *pnd, uint16_t ui16Reg, uint8_t ui8SymbolMask, uint8_t ui8Value);
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int pn53x_decode_firmware_version (struct nfc_device *pnd);
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int pn53x_set_property_int (struct nfc_device *pnd, const nfc_property property, const int value);
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int pn53x_set_property_bool (struct nfc_device *pnd, const nfc_property property, const bool bEnable);
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int pn53x_set_parameters(struct nfc_device *pnd, const uint8_t ui8Value, const bool bEnable);
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int pn53x_set_tx_bits(struct nfc_device *pnd, const uint8_t ui8Bits);
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int pn53x_wrap_frame(const uint8_t *pbtTx, const size_t szTxBits, const uint8_t *pbtTxPar, uint8_t *pbtFrame);
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int pn53x_unwrap_frame(const uint8_t *pbtFrame, const size_t szFrameBits, uint8_t *pbtRx, uint8_t *pbtRxPar);
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int pn53x_decode_target_data(const uint8_t *pbtRawData, size_t szRawData,
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pn53x_type chip_type, nfc_modulation_type nmt,
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nfc_target_info *pnti);
|
||||
int pn53x_read_register(struct nfc_device *pnd, uint16_t ui16Reg, uint8_t *ui8Value);
|
||||
int pn53x_write_register(struct nfc_device *pnd, uint16_t ui16Reg, uint8_t ui8SymbolMask, uint8_t ui8Value);
|
||||
int pn53x_decode_firmware_version(struct nfc_device *pnd);
|
||||
int pn53x_set_property_int(struct nfc_device *pnd, const nfc_property property, const int value);
|
||||
int pn53x_set_property_bool(struct nfc_device *pnd, const nfc_property property, const bool bEnable);
|
||||
|
||||
int pn53x_check_communication (struct nfc_device *pnd);
|
||||
int pn53x_idle (struct nfc_device *pnd);
|
||||
int pn53x_check_communication(struct nfc_device *pnd);
|
||||
int pn53x_idle(struct nfc_device *pnd);
|
||||
|
||||
// NFC device as Initiator functions
|
||||
int pn53x_initiator_init (struct nfc_device *pnd);
|
||||
int pn53x_initiator_select_passive_target (struct nfc_device *pnd,
|
||||
const nfc_modulation nm,
|
||||
const uint8_t *pbtInitData, const size_t szInitData,
|
||||
nfc_target *pnt);
|
||||
int pn53x_initiator_poll_target (struct nfc_device *pnd,
|
||||
const nfc_modulation *pnmModulations, const size_t szModulations,
|
||||
const uint8_t uiPollNr, const uint8_t uiPeriod,
|
||||
nfc_target *pnt);
|
||||
int pn53x_initiator_select_dep_target (struct nfc_device *pnd,
|
||||
const nfc_dep_mode ndm, const nfc_baud_rate nbr,
|
||||
const nfc_dep_info *pndiInitiator,
|
||||
nfc_target *pnt,
|
||||
const int timeout);
|
||||
int pn53x_initiator_transceive_bits (struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTxBits,
|
||||
const uint8_t *pbtTxPar, uint8_t *pbtRx, uint8_t *pbtRxPar);
|
||||
int pn53x_initiator_transceive_bytes (struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx,
|
||||
uint8_t *pbtRx, const size_t szRx, int timeout);
|
||||
int pn53x_initiator_transceive_bits_timed (struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTxBits,
|
||||
const uint8_t *pbtTxPar, uint8_t *pbtRx, uint8_t *pbtRxPar, uint32_t *cycles);
|
||||
int pn53x_initiator_transceive_bytes_timed (struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx,
|
||||
uint8_t *pbtRx, uint32_t *cycles);
|
||||
int pn53x_initiator_deselect_target (struct nfc_device *pnd);
|
||||
int pn53x_initiator_target_is_present (struct nfc_device *pnd, const nfc_target nt);
|
||||
int pn53x_initiator_init(struct nfc_device *pnd);
|
||||
int pn53x_initiator_select_passive_target(struct nfc_device *pnd,
|
||||
const nfc_modulation nm,
|
||||
const uint8_t *pbtInitData, const size_t szInitData,
|
||||
nfc_target *pnt);
|
||||
int pn53x_initiator_poll_target(struct nfc_device *pnd,
|
||||
const nfc_modulation *pnmModulations, const size_t szModulations,
|
||||
const uint8_t uiPollNr, const uint8_t uiPeriod,
|
||||
nfc_target *pnt);
|
||||
int pn53x_initiator_select_dep_target(struct nfc_device *pnd,
|
||||
const nfc_dep_mode ndm, const nfc_baud_rate nbr,
|
||||
const nfc_dep_info *pndiInitiator,
|
||||
nfc_target *pnt,
|
||||
const int timeout);
|
||||
int pn53x_initiator_transceive_bits(struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTxBits,
|
||||
const uint8_t *pbtTxPar, uint8_t *pbtRx, uint8_t *pbtRxPar);
|
||||
int pn53x_initiator_transceive_bytes(struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx,
|
||||
uint8_t *pbtRx, const size_t szRx, int timeout);
|
||||
int pn53x_initiator_transceive_bits_timed(struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTxBits,
|
||||
const uint8_t *pbtTxPar, uint8_t *pbtRx, uint8_t *pbtRxPar, uint32_t *cycles);
|
||||
int pn53x_initiator_transceive_bytes_timed(struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx,
|
||||
uint8_t *pbtRx, uint32_t *cycles);
|
||||
int pn53x_initiator_deselect_target(struct nfc_device *pnd);
|
||||
int pn53x_initiator_target_is_present(struct nfc_device *pnd, const nfc_target nt);
|
||||
|
||||
// NFC device as Target functions
|
||||
int pn53x_target_init (struct nfc_device *pnd, nfc_target *pnt, uint8_t *pbtRx, const size_t szRxLen, int timeout);
|
||||
int pn53x_target_receive_bits (struct nfc_device *pnd, uint8_t *pbtRx, const size_t szRxLen, uint8_t *pbtRxPar);
|
||||
int pn53x_target_receive_bytes (struct nfc_device *pnd, uint8_t *pbtRx, const size_t szRxLen, int timeout);
|
||||
int pn53x_target_send_bits (struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTxBits, const uint8_t *pbtTxPar);
|
||||
int pn53x_target_send_bytes (struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx, int timeout);
|
||||
int pn53x_target_init(struct nfc_device *pnd, nfc_target *pnt, uint8_t *pbtRx, const size_t szRxLen, int timeout);
|
||||
int pn53x_target_receive_bits(struct nfc_device *pnd, uint8_t *pbtRx, const size_t szRxLen, uint8_t *pbtRxPar);
|
||||
int pn53x_target_receive_bytes(struct nfc_device *pnd, uint8_t *pbtRx, const size_t szRxLen, int timeout);
|
||||
int pn53x_target_send_bits(struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTxBits, const uint8_t *pbtTxPar);
|
||||
int pn53x_target_send_bytes(struct nfc_device *pnd, const uint8_t *pbtTx, const size_t szTx, int timeout);
|
||||
|
||||
// Error handling functions
|
||||
const char *pn53x_strerror (const struct nfc_device *pnd);
|
||||
const char *pn53x_strerror(const struct nfc_device *pnd);
|
||||
|
||||
// C wrappers for PN53x commands
|
||||
int pn53x_SetParameters (struct nfc_device *pnd, const uint8_t ui8Value);
|
||||
int pn53x_SAMConfiguration (struct nfc_device *pnd, const pn532_sam_mode mode, int timeout);
|
||||
int pn53x_PowerDown (struct nfc_device *pnd);
|
||||
int pn53x_InListPassiveTarget (struct nfc_device *pnd, const pn53x_modulation pmInitModulation,
|
||||
const uint8_t szMaxTargets, const uint8_t *pbtInitiatorData,
|
||||
const size_t szInitiatorDataLen, uint8_t *pbtTargetsData, size_t *pszTargetsData,
|
||||
int timeout);
|
||||
int pn53x_InDeselect (struct nfc_device *pnd, const uint8_t ui8Target);
|
||||
int pn53x_InRelease (struct nfc_device *pnd, const uint8_t ui8Target);
|
||||
int pn53x_InAutoPoll (struct nfc_device *pnd, const pn53x_target_type *ppttTargetTypes, const size_t szTargetTypes,
|
||||
const uint8_t btPollNr, const uint8_t btPeriod, nfc_target *pntTargets,
|
||||
const int timeout);
|
||||
int pn53x_InJumpForDEP (struct nfc_device *pnd,
|
||||
const nfc_dep_mode ndm, const nfc_baud_rate nbr,
|
||||
const uint8_t *pbtPassiveInitiatorData,
|
||||
const uint8_t *pbtNFCID3i,
|
||||
const uint8_t *pbtGB, const size_t szGB,
|
||||
nfc_target *pnt,
|
||||
const int timeout);
|
||||
int pn53x_TgInitAsTarget (struct nfc_device *pnd, pn53x_target_mode ptm,
|
||||
const uint8_t *pbtMifareParams,
|
||||
const uint8_t *pbtTkt, size_t szTkt,
|
||||
const uint8_t *pbtFeliCaParams,
|
||||
const uint8_t *pbtNFCID3t, const uint8_t *pbtGB, const size_t szGB,
|
||||
uint8_t *pbtRx, const size_t szRxLen, uint8_t *pbtModeByte, int timeout);
|
||||
int pn53x_SetParameters(struct nfc_device *pnd, const uint8_t ui8Value);
|
||||
int pn53x_SAMConfiguration(struct nfc_device *pnd, const pn532_sam_mode mode, int timeout);
|
||||
int pn53x_PowerDown(struct nfc_device *pnd);
|
||||
int pn53x_InListPassiveTarget(struct nfc_device *pnd, const pn53x_modulation pmInitModulation,
|
||||
const uint8_t szMaxTargets, const uint8_t *pbtInitiatorData,
|
||||
const size_t szInitiatorDataLen, uint8_t *pbtTargetsData, size_t *pszTargetsData,
|
||||
int timeout);
|
||||
int pn53x_InDeselect(struct nfc_device *pnd, const uint8_t ui8Target);
|
||||
int pn53x_InRelease(struct nfc_device *pnd, const uint8_t ui8Target);
|
||||
int pn53x_InAutoPoll(struct nfc_device *pnd, const pn53x_target_type *ppttTargetTypes, const size_t szTargetTypes,
|
||||
const uint8_t btPollNr, const uint8_t btPeriod, nfc_target *pntTargets,
|
||||
const int timeout);
|
||||
int pn53x_InJumpForDEP(struct nfc_device *pnd,
|
||||
const nfc_dep_mode ndm, const nfc_baud_rate nbr,
|
||||
const uint8_t *pbtPassiveInitiatorData,
|
||||
const uint8_t *pbtNFCID3i,
|
||||
const uint8_t *pbtGB, const size_t szGB,
|
||||
nfc_target *pnt,
|
||||
const int timeout);
|
||||
int pn53x_TgInitAsTarget(struct nfc_device *pnd, pn53x_target_mode ptm,
|
||||
const uint8_t *pbtMifareParams,
|
||||
const uint8_t *pbtTkt, size_t szTkt,
|
||||
const uint8_t *pbtFeliCaParams,
|
||||
const uint8_t *pbtNFCID3t, const uint8_t *pbtGB, const size_t szGB,
|
||||
uint8_t *pbtRx, const size_t szRxLen, uint8_t *pbtModeByte, int timeout);
|
||||
|
||||
// RFConfiguration
|
||||
int pn53x_RFConfiguration__RF_field (struct nfc_device *pnd, bool bEnable);
|
||||
int pn53x_RFConfiguration__Various_timings (struct nfc_device *pnd, const uint8_t fATR_RES_Timeout, const uint8_t fRetryTimeout);
|
||||
int pn53x_RFConfiguration__MaxRtyCOM (struct nfc_device *pnd, const uint8_t MaxRtyCOM);
|
||||
int pn53x_RFConfiguration__MaxRetries (struct nfc_device *pnd, const uint8_t MxRtyATR, const uint8_t MxRtyPSL, const uint8_t MxRtyPassiveActivation);
|
||||
int pn53x_RFConfiguration__RF_field(struct nfc_device *pnd, bool bEnable);
|
||||
int pn53x_RFConfiguration__Various_timings(struct nfc_device *pnd, const uint8_t fATR_RES_Timeout, const uint8_t fRetryTimeout);
|
||||
int pn53x_RFConfiguration__MaxRtyCOM(struct nfc_device *pnd, const uint8_t MaxRtyCOM);
|
||||
int pn53x_RFConfiguration__MaxRetries(struct nfc_device *pnd, const uint8_t MxRtyATR, const uint8_t MxRtyPSL, const uint8_t MxRtyPassiveActivation);
|
||||
|
||||
// Misc
|
||||
int pn53x_check_ack_frame (struct nfc_device *pnd, const uint8_t *pbtRxFrame, const size_t szRxFrameLen);
|
||||
int pn53x_check_error_frame (struct nfc_device *pnd, const uint8_t *pbtRxFrame, const size_t szRxFrameLen);
|
||||
int pn53x_build_frame (uint8_t *pbtFrame, size_t *pszFrame, const uint8_t *pbtData, const size_t szData);
|
||||
int pn53x_get_supported_modulation (nfc_device *pnd, const nfc_mode mode, const nfc_modulation_type **const supported_mt);
|
||||
int pn53x_get_supported_baud_rate (nfc_device *pnd, const nfc_modulation_type nmt, const nfc_baud_rate **const supported_br);
|
||||
int pn53x_get_information_about (nfc_device *pnd, char *buf, size_t buflen);
|
||||
int pn53x_check_ack_frame(struct nfc_device *pnd, const uint8_t *pbtRxFrame, const size_t szRxFrameLen);
|
||||
int pn53x_check_error_frame(struct nfc_device *pnd, const uint8_t *pbtRxFrame, const size_t szRxFrameLen);
|
||||
int pn53x_build_frame(uint8_t *pbtFrame, size_t *pszFrame, const uint8_t *pbtData, const size_t szData);
|
||||
int pn53x_get_supported_modulation(nfc_device *pnd, const nfc_mode mode, const nfc_modulation_type **const supported_mt);
|
||||
int pn53x_get_supported_baud_rate(nfc_device *pnd, const nfc_modulation_type nmt, const nfc_baud_rate **const supported_br);
|
||||
int pn53x_get_information_about(nfc_device *pnd, char *buf, size_t buflen);
|
||||
|
||||
void pn53x_data_new (struct nfc_device *pnd, const struct pn53x_io *io);
|
||||
void pn53x_data_free (struct nfc_device *pnd);
|
||||
void pn53x_data_new(struct nfc_device *pnd, const struct pn53x_io *io);
|
||||
void pn53x_data_free(struct nfc_device *pnd);
|
||||
|
||||
#endif // __NFC_CHIPS_PN53X_H__
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue