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Fix writeback cache size and some typo.

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This commit is contained in:
Romuald Conty 2011-05-09 19:55:22 +00:00
parent 009d851771
commit b3cade2db2
2 changed files with 13 additions and 13 deletions
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16
libnfc/chips/pn53x.c
View file

@ -508,15 +508,15 @@ pn53x_write_register (nfc_device_t * pnd, const uint16_t ui16RegisterAddress, co
bool bool
pn53x_writeback_register (nfc_device_t * pnd) pn53x_writeback_register (nfc_device_t * pnd)
{ {
// TODO Check at each step (ReadRegister, WriteRegister) if we don't exceeded max supported frame lenght // TODO Check at each step (ReadRegister, WriteRegister) if we didn't exceed max supported frame length
uint8_t abtCmd[PN53x_EXTENDED_FRAME__DATA_MAX_LEN] = { ReadRegister }; uint8_t abtCmd[PN53x_EXTENDED_FRAME__DATA_MAX_LEN] = { ReadRegister };
size_t szCmd = 1; size_t szCmd = 1;
// First step, it look for registers which need to be readed before applying the requested mask // First step, it looks for registers to be readed before applying the requested mask
CHIP_DATA (pnd)->wb_trigged = false; CHIP_DATA (pnd)->wb_trigged = false;
for (size_t n = 0; n < PN53X_CACHE_REGISTER_MAX_ADDRESS - PN53X_CACHE_REGISTER_MIN_ADDRESS; n++) { for (size_t n = 0; n < PN53X_CACHE_REGISTER_SIZE; n++) {
if ((CHIP_DATA (pnd)->wb_mask[n]) && (CHIP_DATA (pnd)->wb_mask[n] != 0xff)) { if ((CHIP_DATA (pnd)->wb_mask[n]) && (CHIP_DATA (pnd)->wb_mask[n] != 0xff)) {
// This register need to be readed: mask is present but does not cover full data width (ie. mask != 0xff) // This register needs to be readed: mask is present but does not cover full data width (ie. mask != 0xff)
const uint16_t pn53x_register_address = PN53X_CACHE_REGISTER_MIN_ADDRESS + n; const uint16_t pn53x_register_address = PN53X_CACHE_REGISTER_MIN_ADDRESS + n;
abtCmd[szCmd++] = pn53x_register_address >> 8; abtCmd[szCmd++] = pn53x_register_address >> 8;
abtCmd[szCmd++] = pn53x_register_address & 0xff; abtCmd[szCmd++] = pn53x_register_address & 0xff;
@ -524,10 +524,10 @@ pn53x_writeback_register (nfc_device_t * pnd)
} }
if (szCmd > 1) { if (szCmd > 1) {
// It need to read some registers // It needs to read some registers
uint8_t abtRes[PN53x_EXTENDED_FRAME__DATA_MAX_LEN]; uint8_t abtRes[PN53x_EXTENDED_FRAME__DATA_MAX_LEN];
size_t szRes = sizeof(abtRes); size_t szRes = sizeof(abtRes);
// Transceive the previously constructed ReadRegister command // It transceives the previously constructed ReadRegister command
if (!pn53x_transceive (pnd, abtCmd, szCmd, abtRes, &szRes)) { if (!pn53x_transceive (pnd, abtCmd, szCmd, abtRes, &szRes)) {
return false; return false;
} }
@ -536,7 +536,7 @@ pn53x_writeback_register (nfc_device_t * pnd)
// PN533 prepends its answer by a status byte // PN533 prepends its answer by a status byte
i = 1; i = 1;
} }
for (size_t n = 0; n < PN53X_CACHE_REGISTER_MAX_ADDRESS - PN53X_CACHE_REGISTER_MIN_ADDRESS; n++) { for (size_t n = 0; n < PN53X_CACHE_REGISTER_SIZE; n++) {
if ((CHIP_DATA (pnd)->wb_mask[n]) && (CHIP_DATA (pnd)->wb_mask[n] != 0xff)) { if ((CHIP_DATA (pnd)->wb_mask[n]) && (CHIP_DATA (pnd)->wb_mask[n] != 0xff)) {
CHIP_DATA (pnd)->wb_data[n] = ((CHIP_DATA (pnd)->wb_data[n] & CHIP_DATA (pnd)->wb_mask[n]) | (abtRes[i] & (~CHIP_DATA (pnd)->wb_mask[n]))); CHIP_DATA (pnd)->wb_data[n] = ((CHIP_DATA (pnd)->wb_data[n] & CHIP_DATA (pnd)->wb_mask[n]) | (abtRes[i] & (~CHIP_DATA (pnd)->wb_mask[n])));
if (CHIP_DATA (pnd)->wb_data[n] != abtRes[i]) { if (CHIP_DATA (pnd)->wb_data[n] != abtRes[i]) {
@ -552,7 +552,7 @@ pn53x_writeback_register (nfc_device_t * pnd)
// Now, the writeback-cache only have masks with 0xff, we can start to WriteRegister // Now, the writeback-cache only have masks with 0xff, we can start to WriteRegister
szCmd = 1; szCmd = 1;
abtCmd[0] = WriteRegister; abtCmd[0] = WriteRegister;
for (size_t n = 0; n < PN53X_CACHE_REGISTER_MAX_ADDRESS - PN53X_CACHE_REGISTER_MIN_ADDRESS; n++) { for (size_t n = 0; n < PN53X_CACHE_REGISTER_SIZE; n++) {
if (CHIP_DATA (pnd)->wb_mask[n] == 0xff) { if (CHIP_DATA (pnd)->wb_mask[n] == 0xff) {
const uint16_t pn53x_register_address = PN53X_CACHE_REGISTER_MIN_ADDRESS + n; const uint16_t pn53x_register_address = PN53X_CACHE_REGISTER_MIN_ADDRESS + n;
abtCmd[szCmd++] = pn53x_register_address >> 8; abtCmd[szCmd++] = pn53x_register_address >> 8;

10
libnfc/chips/pn53x.h
View file

@ -152,9 +152,9 @@ struct pn53x_io {
}; };
/* defines */ /* defines */
#define PN53X_CACHE_REGISTER_MIN_ADDRESS PN53X_REG_CIU_Mode #define PN53X_CACHE_REGISTER_MIN_ADDRESS PN53X_REG_CIU_Mode
#define PN53X_CACHE_REGISTER_MAX_ADDRESS PN53X_REG_CIUColl #define PN53X_CACHE_REGISTER_MAX_ADDRESS PN53X_REG_CIUColl
#define PN53X_CACHE_REGISTER_SIZE ((PN53X_CACHE_REGISTER_MAX_ADDRESS - PN53X_CACHE_REGISTER_MIN_ADDRESS) + 1)
struct pn53x_data { struct pn53x_data {
/** Chip type (PN531, PN532 or PN533)*/ /** Chip type (PN531, PN532 or PN533)*/
pn53x_type type; pn53x_type type;
@ -175,8 +175,8 @@ struct pn53x_data {
/** Interframe timer correction */ /** Interframe timer correction */
int16_t timer_correction; int16_t timer_correction;
/** WriteBack cache */ /** WriteBack cache */
uint8_t wb_data[PN53X_CACHE_REGISTER_MAX_ADDRESS-PN53X_CACHE_REGISTER_MIN_ADDRESS]; uint8_t wb_data[PN53X_CACHE_REGISTER_SIZE];
uint8_t wb_mask[PN53X_CACHE_REGISTER_MAX_ADDRESS-PN53X_CACHE_REGISTER_MIN_ADDRESS]; uint8_t wb_mask[PN53X_CACHE_REGISTER_SIZE];
bool wb_trigged; bool wb_trigged;
}; };