chips/pn53x: print a debug trace when reading PN53x registers.
This commit is contained in:
Romuald Conty
parent
579102bd7b
commit
cad3dc652d
2 changed files with 165 additions and 0 deletions
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@ -187,6 +187,7 @@ static const pn53x_command pn53x_commands[] = {
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PNCMD( TgGetTargetStatus, PN531|PN532|PN533 ),
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};
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// SFR part
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#define _BV( X ) (1 << X)
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#define P30 0
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@ -196,4 +197,165 @@ static const pn53x_command pn53x_commands[] = {
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#define P34 4
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#define P35 5
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// Registers part
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#ifdef DEBUG
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typedef struct {
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uint16_t ui16Address;
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const char * abtRegisterText;
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const char * abtRegisterDescription;
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} pn53x_register;
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#endif
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/*
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#define PN531 0x01
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#define PN532 0x02
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#define PN533 0X04
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*/
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#ifndef DEBUG
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# define PNREG_DBG( X ) do { \
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} while(0)
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#else
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# define PNREG( X, Y ) { X , #X, Y }
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# define PNREG_DBG( X ) do { \
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for (size_t i=0; i<(sizeof(pn53x_registers)/sizeof(pn53x_register)); i++) { \
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if ( X == pn53x_registers[i].ui16Address ) { \
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DBG( "%s (%s)", pn53x_registers[i].abtRegisterText, pn53x_registers[i].abtRegisterDescription ); \
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break; \
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} \
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} \
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} while(0)
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#endif
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// Register addresses
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#define PN53X_REG_CIU_Mode 0x6301
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#define PN53X_REG_CIU_TxMode 0x6303
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#define PN53X_REG_CIU_RxMode 0x6303
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#define PN53X_REG_CIU_TxControl 0x6304
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#define PN53X_REG_CIU_TxAuto 0x6305
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#define PN53X_REG_CIU_TxSel 0x6306
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#define PN53X_REG_CIU_RxSel 0x6307
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#define PN53X_REG_CIU_RxThreshold 0x6308
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#define PN53X_REG_CIU_Demod 0x6309
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#define PN53X_REG_CIU_FelNFC1 0x630A
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#define PN53X_REG_CIU_FelNFC2 0x630B
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#define PN53X_REG_CIU_MifNFC 0x630C
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#define PN53X_REG_CIU_ManualRCV 0x630D
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#define PN53X_REG_CIU_TypeB 0x630E
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// #define PN53X_REG_- 0x630F
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// #define PN53X_REG_- 0x6310
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#define PN53X_REG_CIU_CRCResultMSB 0x6311
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#define PN53X_REG_CIU_CRCResultLSB 0x6312
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#define PN53X_REG_CIU_GsNOFF 0x6313
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#define PN53X_REG_CIU_ModWidth 0x6314
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#define PN53X_REG_CIU_TxBitPhase 0x6315
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#define PN53X_REG_CIU_RFCfg 0x6316
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#define PN53X_REG_CIU_GsNOn 0x6317
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#define PN53X_REG_CIU_CWGsP 0x6318
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#define PN53X_REG_CIU_ModGsP 0x6319
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#define PN53X_REG_CIU_TMode 0x631A
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#define PN53X_REG_CIU_TPrescaler 0x631B
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#define PN53X_REG_CIU_TReloadVal_hi 0x631C
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#define PN53X_REG_CIU_TReloadVal_lo 0x631D
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#define PN53X_REG_CIU_TCounterVal_hi 0x631E
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#define PN53X_REG_CIU_TCounterVal_lo 0x631F
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// #define PN53X_REG_- 0x6320
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#define PN53X_REG_CIU_TestSel1 0x6321
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#define PN53X_REG_CIU_TestSel2 0x6322
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#define PN53X_REG_CIU_TestPinEn 0x6323
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#define PN53X_REG_CIU_TestPinValue 0x6324
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#define PN53X_REG_CIU_TestBus 0x6325
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#define PN53X_REG_CIU_AutoTest 0x6326
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#define PN53X_REG_CIU_Version 0x6327
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#define PN53X_REG_CIU_AnalogTest 0x6328
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#define PN53X_REG_CIU_TestDAC1 0x6329
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#define PN53X_REG_CIU_TestDAC2 0x632A
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#define PN53X_REG_CIU_TestADC 0x632B
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// #define PN53X_REG_- 0x632C
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// #define PN53X_REG_- 0x632D
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// #define PN53X_REG_- 0x632E
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#define PN53X_REG_CIU_RFlevelDet 0x632F
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#define PN53X_REG_CIU_SIC_CLK_en 0x6330
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#define PN53X_REG_CIU_Command 0x6331
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#define PN53X_REG_CIU_CommIEn 0x6332
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#define PN53X_REG_CIU_DivIEn 0x6333
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#define PN53X_REG_CIU_CommIrq 0x6334
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#define PN53X_REG_CIU_DivIrq 0x6335
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#define PN53X_REG_CIU_Error 0x6336
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#define PN53X_REG_CIU_Status1 0x6337
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#define PN53X_REG_CIU_Status2 0x6338
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#define PN53X_REG_CIU_FIFOData 0x6339
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#define PN53X_REG_CIUFIFOLevel 0x633A
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#define PN53X_REG_CIUWaterLevel 0x633B
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#define PN53X_REG_CIUControl 0x633C
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#define PN53X_REG_CIUBitFraming 0x633D
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#define PN53X_REG_CIUColl 0x633E
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#ifdef DEBUG
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static const pn53x_register pn53x_registers[] = {
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PNREG (PN53X_REG_CIU_Mode, "Defines general modes for transmitting and receiving"),
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PNREG (PN53X_REG_CIU_TxMode, "Defines the transmission data rate and framing during transmission"),
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PNREG (PN53X_REG_CIU_RxMode, "Defines the transmission data rate and framing during receiving"),
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PNREG (PN53X_REG_CIU_TxControl, "Controls the logical behaviour of the antenna driver pins TX1 and TX2"),
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PNREG (PN53X_REG_CIU_TxAuto, "Controls the settings of the antenna driver"),
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PNREG (PN53X_REG_CIU_TxSel, "Selects the internal sources for the antenna driver"),
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PNREG (PN53X_REG_CIU_RxSel, "Selects internal receiver settings"),
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PNREG (PN53X_REG_CIU_RxThreshold, "Selects thresholds for the bit decoder"),
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PNREG (PN53X_REG_CIU_Demod, "Defines demodulator settings"),
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PNREG (PN53X_REG_CIU_FelNFC1, "Defines the length of the valid range for the received frame"),
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PNREG (PN53X_REG_CIU_FelNFC2, "Defines the length of the valid range for the received frame"),
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PNREG (PN53X_REG_CIU_MifNFC, "Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit/s"),
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PNREG (PN53X_REG_CIU_ManualRCV, "Allows manual fine tuning of the internal receiver"),
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PNREG (PN53X_REG_CIU_TypeB, "Configure the ISO/IEC 14443 type B"),
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// PNREG (PN53X_REG_-, "Reserved"),
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// PNREG (PN53X_REG_-, "Reserved"),
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PNREG (PN53X_REG_CIU_CRCResultMSB, "Shows the actual MSB values of the CRC calculation"),
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PNREG (PN53X_REG_CIU_CRCResultLSB, "Shows the actual LSB values of the CRC calculation"),
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PNREG (PN53X_REG_CIU_GsNOFF, "Selects the conductance of the antenna driver pins TX1 and TX2 for load modulation when own RF field is switched OFF"),
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PNREG (PN53X_REG_CIU_ModWidth, "Controls the setting of the width of the Miller pause"),
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PNREG (PN53X_REG_CIU_TxBitPhase, "Bit synchronization at 106 kbit/s"),
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PNREG (PN53X_REG_CIU_RFCfg, "Configures the receiver gain and RF level"),
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PNREG (PN53X_REG_CIU_GsNOn, "Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when own RF field is switched ON"),
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PNREG (PN53X_REG_CIU_CWGsP, "Selects the conductance of the antenna driver pins TX1 and TX2 when not in modulation phase"),
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PNREG (PN53X_REG_CIU_ModGsP, "Selects the conductance of the antenna driver pins TX1 and TX2 when in modulation phase"),
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PNREG (PN53X_REG_CIU_TMode, "Defines settings for the internal timer"),
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PNREG (PN53X_REG_CIU_TPrescaler, "Defines settings for the internal timer"),
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PNREG (PN53X_REG_CIU_TReloadVal_hi, "Describes the 16-bit long timer reload value (Higher 8 bits)"),
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PNREG (PN53X_REG_CIU_TReloadVal_lo, "Describes the 16-bit long timer reload value (Lower 8 bits)"),
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PNREG (PN53X_REG_CIU_TCounterVal_hi, "Describes the 16-bit long timer actual value (Higher 8 bits)"),
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PNREG (PN53X_REG_CIU_TCounterVal_lo, "Describes the 16-bit long timer actual value (Lower 8 bits)"),
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// PNREG (PN53X_REG_-, "Reserved"),
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PNREG (PN53X_REG_CIU_TestSel1, "General test signals configuration"),
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PNREG (PN53X_REG_CIU_TestSel2, "General test signals configuration and PRBS control"),
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PNREG (PN53X_REG_CIU_TestPinEn, "Enables test signals output on pins."),
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PNREG (PN53X_REG_CIU_TestPinValue, "Defines the values for the 8-bit parallel bus when it is used as I/O bus"),
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PNREG (PN53X_REG_CIU_TestBus, "Shows the status of the internal test bus"),
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PNREG (PN53X_REG_CIU_AutoTest, "Controls the digital self-test"),
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PNREG (PN53X_REG_CIU_Version, "Shows the CIU version"),
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PNREG (PN53X_REG_CIU_AnalogTest, "Controls the pins AUX1 and AUX2"),
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PNREG (PN53X_REG_CIU_TestDAC1, "Defines the test value for the TestDAC1"),
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PNREG (PN53X_REG_CIU_TestDAC2, "Defines the test value for the TestDAC2"),
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PNREG (PN53X_REG_CIU_TestADC, "Show the actual value of ADC I and Q"),
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// PNREG (PN53X_REG_-, "Reserved for tests"),
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// PNREG (PN53X_REG_-, "Reserved for tests"),
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// PNREG (PN53X_REG_-, "Reserved for tests"),
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PNREG (PN53X_REG_CIU_RFlevelDet, "Power down of the RF level detector"),
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PNREG (PN53X_REG_CIU_SIC_CLK_en, "Enables the use of secure IC clock on P34 / SIC_CLK"),
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PNREG (PN53X_REG_CIU_Command, "Starts and stops the command execution"),
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PNREG (PN53X_REG_CIU_CommIEn, "Control bits to enable and disable the passing of interrupt requests"),
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PNREG (PN53X_REG_CIU_DivIEn, "Controls bits to enable and disable the passing of interrupt requests"),
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PNREG (PN53X_REG_CIU_CommIrq, "Contains common CIU interrupt request flags"),
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PNREG (PN53X_REG_CIU_DivIrq, "Contains miscellaneous interrupt request flags"),
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PNREG (PN53X_REG_CIU_Error, "Error flags showing the error status of the last command executed"),
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PNREG (PN53X_REG_CIU_Status1, "Contains status flags of the CRC, Interrupt Request System and FIFO buffer"),
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PNREG (PN53X_REG_CIU_Status2, "Contain status flags of the receiver, transmitter and Data Mode Detector"),
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PNREG (PN53X_REG_CIU_FIFOData, "In- and output of 64 byte FIFO buffer"),
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PNREG (PN53X_REG_CIUFIFOLevel, "Indicates the number of bytes stored in the FIFO"),
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PNREG (PN53X_REG_CIUWaterLevel, "Defines the thresholds for FIFO under- and overflow warning"),
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PNREG (PN53X_REG_CIUControl, "Contains miscellaneous control bits"),
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PNREG (PN53X_REG_CIUBitFraming, "Adjustments for bit oriented frames"),
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PNREG (PN53X_REG_CIUColl, "Defines the first bit collision detected on the RF interface"),
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};
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#endif
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#endif /* __PN53X_INTERNAL_H__ */
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@ -409,6 +409,9 @@ pn53x_read_register (nfc_device_t * pnd, uint16_t ui16Reg, uint8_t * ui8Value)
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byte_t abtRegValue[2];
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size_t szRegValue = sizeof (abtRegValue);
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PNREG_DBG (ui16Reg);
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if (pn53x_transceive (pnd, abtCmd, sizeof (abtCmd), abtRegValue, &szRegValue)) {
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if (CHIP_DATA(pnd)->type == PN533) {
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// PN533 prepends its answer by a status byte
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