chips/pn53x: remove double defines for pn53x registers.
This commit is contained in:
Romuald Conty
parent
e4dfa75045
commit
d37b917352
5 changed files with 74 additions and 88 deletions
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@ -226,6 +226,7 @@ typedef struct {
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#endif
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// Register addresses
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#define PN53X_REG_Control_switch_rng 0x6106
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#define PN53X_REG_CIU_Mode 0x6301
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#define PN53X_REG_CIU_TxMode 0x6302
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#define PN53X_REG_CIU_RxMode 0x6303
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@ -283,11 +284,11 @@ typedef struct {
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#define PN53X_REG_CIU_Status1 0x6337
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#define PN53X_REG_CIU_Status2 0x6338
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#define PN53X_REG_CIU_FIFOData 0x6339
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#define PN53X_REG_CIUFIFOLevel 0x633A
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#define PN53X_REG_CIUWaterLevel 0x633B
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#define PN53X_REG_CIUControl 0x633C
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#define PN53X_REG_CIUBitFraming 0x633D
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#define PN53X_REG_CIUColl 0x633E
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#define PN53X_REG_CIU_FIFOLevel 0x633A
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#define PN53X_REG_CIU_WaterLevel 0x633B
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#define PN53X_REG_CIU_Control 0x633C
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#define PN53X_REG_CIU_BitFraming 0x633D
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#define PN53X_REG_CIU_Coll 0x633E
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#define PN53X_SFR_P3 0xFFB0
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@ -358,11 +359,11 @@ static const pn53x_register pn53x_registers[] = {
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PNREG (PN53X_REG_CIU_Status1, "Contains status flags of the CRC, Interrupt Request System and FIFO buffer"),
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PNREG (PN53X_REG_CIU_Status2, "Contain status flags of the receiver, transmitter and Data Mode Detector"),
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PNREG (PN53X_REG_CIU_FIFOData, "In- and output of 64 byte FIFO buffer"),
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PNREG (PN53X_REG_CIUFIFOLevel, "Indicates the number of bytes stored in the FIFO"),
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PNREG (PN53X_REG_CIUWaterLevel, "Defines the thresholds for FIFO under- and overflow warning"),
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PNREG (PN53X_REG_CIUControl, "Contains miscellaneous control bits"),
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PNREG (PN53X_REG_CIUBitFraming, "Adjustments for bit oriented frames"),
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PNREG (PN53X_REG_CIUColl, "Defines the first bit collision detected on the RF interface"),
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PNREG (PN53X_REG_CIU_FIFOLevel, "Indicates the number of bytes stored in the FIFO"),
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PNREG (PN53X_REG_CIU_WaterLevel, "Defines the thresholds for FIFO under- and overflow warning"),
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PNREG (PN53X_REG_CIU_Control, "Contains miscellaneous control bits"),
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PNREG (PN53X_REG_CIU_BitFraming, "Adjustments for bit oriented frames"),
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PNREG (PN53X_REG_CIU_Coll, "Defines the first bit collision detected on the RF interface"),
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// SFR
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PNREG (PN53X_SFR_P3CFGA, "Port 3 configuration"),
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@ -95,7 +95,7 @@ pn53x_reset_settings(nfc_device_t * pnd)
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{
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// Reset the ending transmission bits register, it is unknown what the last tranmission used there
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CHIP_DATA (pnd)->ui8TxBits = 0;
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if (!pn53x_write_register (pnd, REG_CIU_BIT_FRAMING, SYMBOL_TX_LAST_BITS, 0x00)) {
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_TX_LAST_BITS, 0x00)) {
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return false;
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}
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return true;
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@ -193,7 +193,7 @@ pn53x_set_tx_bits (nfc_device_t * pnd, const uint8_t ui8Bits)
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// Test if we need to update the transmission bits register setting
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if (CHIP_DATA (pnd)->ui8TxBits != ui8Bits) {
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// Set the amount of transmission bits in the PN53X chip register
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if (!pn53x_write_register (pnd, REG_CIU_BIT_FRAMING, SYMBOL_TX_LAST_BITS, ui8Bits))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_TX_LAST_BITS, ui8Bits))
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return false;
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// Store the new setting
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@ -626,9 +626,9 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
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// Enable or disable automatic receiving/sending of CRC bytes
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// TX and RX are both represented by the symbol 0x80
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btValue = (bEnable) ? 0x80 : 0x00;
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if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_CRC_ENABLE, btValue))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_CRC_ENABLE, btValue))
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return false;
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if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_CRC_ENABLE, btValue))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_CRC_ENABLE, btValue))
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return false;
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pnd->bCrc = bEnable;
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break;
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@ -636,7 +636,7 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
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case NDO_HANDLE_PARITY:
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// Handle parity bit by PN53X chip or parse it as data bit
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btValue = (bEnable) ? 0x00 : SYMBOL_PARITY_DISABLE;
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if (!pn53x_write_register (pnd, REG_CIU_MANUAL_RCV, SYMBOL_PARITY_DISABLE, btValue))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_ManualRCV, SYMBOL_PARITY_DISABLE, btValue))
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return false;
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pnd->bPar = bEnable;
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break;
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@ -655,7 +655,7 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
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case NDO_ACTIVATE_CRYPTO1:
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btValue = (bEnable) ? SYMBOL_MF_CRYPTO1_ON : 0x00;
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if (!pn53x_write_register (pnd, REG_CIU_STATUS2, SYMBOL_MF_CRYPTO1_ON, btValue))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_Status2, SYMBOL_MF_CRYPTO1_ON, btValue))
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return false;
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break;
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@ -679,13 +679,13 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
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case NDO_ACCEPT_INVALID_FRAMES:
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btValue = (bEnable) ? SYMBOL_RX_NO_ERROR : 0x00;
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if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_NO_ERROR, btValue))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_NO_ERROR, btValue))
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return false;
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break;
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case NDO_ACCEPT_MULTIPLE_FRAMES:
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btValue = (bEnable) ? SYMBOL_RX_MULTIPLE : 0x00;
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if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_MULTIPLE, btValue))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_MULTIPLE, btValue))
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return false;
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return true;
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break;
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@ -702,14 +702,14 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
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return true;
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}
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// Force pn53x to be in ISO14443-A mode
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if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_FRAMING, 0x00)) {
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_FRAMING, 0x00)) {
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return false;
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}
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if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_FRAMING, 0x00)) {
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_FRAMING, 0x00)) {
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return false;
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}
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// Set the PN53X to force 100% ASK Modified miller decoding (default for 14443A cards)
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if (!pn53x_write_register (pnd, REG_CIU_TX_AUTO, SYMBOL_FORCE_100_ASK, 0x40))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxAuto, SYMBOL_FORCE_100_ASK, 0x40))
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return false;
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return true;
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@ -721,10 +721,10 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
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return true;
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}
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// Force pn53x to be in ISO14443-B mode
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if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_FRAMING, 0x03)) {
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_FRAMING, 0x03)) {
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return false;
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}
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if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_FRAMING, 0x03)) {
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_FRAMING, 0x03)) {
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return false;
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}
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@ -737,10 +737,10 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
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return true;
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}
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// Force pn53x to be at 106 kbps
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if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_SPEED, 0x00)) {
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_SPEED, 0x00)) {
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return false;
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}
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if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_SPEED, 0x00)) {
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_SPEED, 0x00)) {
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return false;
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}
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@ -820,7 +820,7 @@ pn53x_initiator_init (nfc_device_t * pnd)
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pn53x_reset_settings(pnd);
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// Configure the PN53X to be an Initiator or Reader/Writer
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if (!pn53x_write_register (pnd, REG_CIU_CONTROL, SYMBOL_INITIATOR, 0x10))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_Control, SYMBOL_INITIATOR, 0x10))
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return false;
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CHIP_DATA (pnd)->operating_mode = INITIATOR;
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@ -1006,7 +1006,7 @@ pn53x_initiator_transceive_bits (nfc_device_t * pnd, const byte_t * pbtTx, const
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return false;
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// Get the last bit-count that is stored in the received byte
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if (!pn53x_read_register (pnd, REG_CIU_CONTROL, &ui8rcc))
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if (!pn53x_read_register (pnd, PN53X_REG_CIU_Control, &ui8rcc))
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return false;
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ui8Bits = ui8rcc & SYMBOL_RX_LAST_BITS;
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@ -1082,10 +1082,10 @@ void __pn53x_init_timer(nfc_device_t * pnd)
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uint16_t prescaler = 0;
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uint16_t reloadval = 0xFFFF;
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// Initialize timer
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pn53x_write_register (pnd, REG_CIU_TMODE, 0xFF, SYMBOL_TAUTO | ((prescaler >> 8) & SYMBOL_TPRESCALERHI));
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pn53x_write_register (pnd, REG_CIU_TPRESCALER, 0xFF, (prescaler & SYMBOL_TPRESCALERLO));
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pn53x_write_register (pnd, REG_CIU_TRELOADVALHI, 0xFF, (reloadval >> 8) & 0xFF);
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pn53x_write_register (pnd, REG_CIU_TRELOADVALLO, 0xFF, reloadval & 0xFF);
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pn53x_write_register (pnd, PN53X_REG_CIU_TMode, 0xFF, SYMBOL_TAUTO | ((prescaler >> 8) & SYMBOL_TPRESCALERHI));
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pn53x_write_register (pnd, PN53X_REG_CIU_TPrescaler, 0xFF, (prescaler & SYMBOL_TPRESCALERLO));
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pn53x_write_register (pnd, PN53X_REG_CIU_TReloadVal_hi, 0xFF, (reloadval >> 8) & 0xFF);
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pn53x_write_register (pnd, PN53X_REG_CIU_TReloadVal_lo, 0xFF, reloadval & 0xFF);
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}
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uint16_t __pn53x_get_timer(nfc_device_t * pnd, const uint8_t last_cmd_byte)
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@ -1094,8 +1094,8 @@ uint16_t __pn53x_get_timer(nfc_device_t * pnd, const uint8_t last_cmd_byte)
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uint8_t counter_hi, counter_lo;
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uint16_t counter, cycles;
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// Read timer
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pn53x_read_register (pnd, REG_CIU_TCOUNTERVALHI, &counter_hi);
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pn53x_read_register (pnd, REG_CIU_TCOUNTERVALLO, &counter_lo);
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pn53x_read_register (pnd, PN53X_REG_CIU_TCounterVal_hi, &counter_hi);
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pn53x_read_register (pnd, PN53X_REG_CIU_TCounterVal_lo, &counter_lo);
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counter = counter_hi;
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counter = (counter << 8) + counter_lo;
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if (counter == 0) {
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@ -1160,14 +1160,14 @@ pn53x_initiator_transceive_bits_timed (nfc_device_t * pnd, const byte_t * pbtTx,
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// E.g. on SCL3711 timer settings are reset by 0x42 InCommunicateThru command to:
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// 631a=82 631b=a5 631c=02 631d=00
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// Prepare FIFO
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pn53x_WriteRegister (pnd, REG_CIU_COMMAND, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE);
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pn53x_WriteRegister (pnd, REG_CIU_FIFOLEVEL, SYMBOL_FLUSH_BUFFER);
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_Command, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE);
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOLevel, SYMBOL_FLUSH_BUFFER);
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for (i=0; i< ((szTxBits / 8) + 1); i++) {
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pn53x_WriteRegister (pnd, REG_CIU_FIFODATA, pbtTx[i]);
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOData, pbtTx[i]);
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}
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// Send data
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pn53x_WriteRegister (pnd, REG_CIU_BIT_FRAMING, SYMBOL_START_SEND | ((szTxBits % 8) & SYMBOL_TX_LAST_BITS));
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_START_SEND | ((szTxBits % 8) & SYMBOL_TX_LAST_BITS));
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// Recv data
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*pszRxBits = 0;
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@ -1176,16 +1176,16 @@ pn53x_initiator_transceive_bits_timed (nfc_device_t * pnd, const byte_t * pbtTx,
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// responses coming very late anyway.
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// Ideally we should implement a real timer here too but looping a few times is good enough.
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for (i=0; i<4; i++) {
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pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz);
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pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
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if (sz > 0)
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break;
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}
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while (1) {
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for (i=0; i<sz; i++) {
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pn53x_read_register (pnd, REG_CIU_FIFODATA, &(pbtRx[i+*pszRxBits]));
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pn53x_read_register (pnd, PN53X_REG_CIU_FIFOData, &(pbtRx[i+*pszRxBits]));
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}
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*pszRxBits += (size_t) (sz & SYMBOL_FIFO_LEVEL);
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pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz);
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pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
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if (sz == 0)
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break;
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}
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@ -1222,14 +1222,14 @@ pn53x_initiator_transceive_bytes_timed (nfc_device_t * pnd, const byte_t * pbtTx
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// E.g. on SCL3711 timer settings are reset by 0x42 InCommunicateThru command to:
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// 631a=82 631b=a5 631c=02 631d=00
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// Prepare FIFO
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pn53x_WriteRegister (pnd, REG_CIU_COMMAND, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE);
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pn53x_WriteRegister (pnd, REG_CIU_FIFOLEVEL, SYMBOL_FLUSH_BUFFER);
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_Command, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE);
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOLevel, SYMBOL_FLUSH_BUFFER);
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for (i=0; i< szTx; i++) {
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pn53x_WriteRegister (pnd, REG_CIU_FIFODATA, pbtTx[i]);
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOData, pbtTx[i]);
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}
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// Send data
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pn53x_WriteRegister (pnd, REG_CIU_BIT_FRAMING, SYMBOL_START_SEND);
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pn53x_WriteRegister (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_START_SEND);
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// Recv data
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*pszRx = 0;
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@ -1238,16 +1238,16 @@ pn53x_initiator_transceive_bytes_timed (nfc_device_t * pnd, const byte_t * pbtTx
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// responses coming very late anyway.
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// Ideally we should implement a real timer here too but looping a few times is good enough.
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for (i=0; i<4; i++) {
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pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz);
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pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
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if (sz > 0)
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break;
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}
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while (1) {
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for (i=0; i<sz; i++) {
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pn53x_read_register (pnd, REG_CIU_FIFODATA, &(pbtRx[i+*pszRx]));
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pn53x_read_register (pnd, PN53X_REG_CIU_FIFOData, &(pbtRx[i+*pszRx]));
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}
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*pszRx += (size_t) (sz & SYMBOL_FIFO_LEVEL);
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pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz);
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pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
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if (sz == 0)
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break;
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}
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@ -1323,7 +1323,7 @@ pn53x_target_init (nfc_device_t * pnd, nfc_target_t * pnt, byte_t * pbtRx, size_
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}
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// Let the PN53X be activated by the RF level detector from power down mode
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if (!pn53x_write_register (pnd, REG_CIU_TX_AUTO, SYMBOL_INITIAL_RF_ON, 0x04))
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if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxAuto, SYMBOL_INITIAL_RF_ON, 0x04))
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return false;
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byte_t abtMifareParams[6];
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@ -1503,7 +1503,7 @@ pn53x_target_receive_bits (nfc_device_t * pnd, byte_t * pbtRx, size_t * pszRxBit
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// Get the last bit-count that is stored in the received byte
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uint8_t ui8rcc;
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if (!pn53x_read_register (pnd, REG_CIU_CONTROL, &ui8rcc))
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if (!pn53x_read_register (pnd, PN53X_REG_CIU_Control, &ui8rcc))
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return false;
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uint8_t ui8Bits = ui8rcc & SYMBOL_RX_LAST_BITS;
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@ -30,9 +30,8 @@
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# include <nfc/nfc-types.h>
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# include "pn53x-internal.h"
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// TODO Remove double register address defines
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// Registers and symbols masks used to covers parts within a register
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||||
# define REG_CIU_TX_MODE 0x6302
|
||||
// PN53X_REG_CIU_TxMode
|
||||
# define SYMBOL_TX_CRC_ENABLE 0x80
|
||||
# define SYMBOL_TX_SPEED 0x70
|
||||
// TX_FRAMING bits explanation:
|
||||
|
|
@ -42,12 +41,12 @@
|
|||
// 11 : ISO/IEC 14443B
|
||||
# define SYMBOL_TX_FRAMING 0x03
|
||||
|
||||
# define REG_CONTROL_SWITCH_RNG 0x6106
|
||||
// PN53X_REG_Control_switch_rng
|
||||
# define SYMBOL_CURLIMOFF 0x08 /* When set to 1, the 100 mA current limitations is desactivated. */
|
||||
# define SYMBOL_SIC_SWITCH_EN 0x10 /* When set to logic 1, the SVDD switch is enabled and the SVDD output delivers power to secure IC and internal pads (SIGIN, SIGOUT and P34). */
|
||||
# define SYMBOL_RANDOM_DATAREADY 0x02 /* When set to logic 1, a new random number is available. */
|
||||
|
||||
# define REG_CIU_RX_MODE 0x6303
|
||||
// PN53X_REG_CIU_RxMode
|
||||
# define SYMBOL_RX_CRC_ENABLE 0x80
|
||||
# define SYMBOL_RX_SPEED 0x70
|
||||
# define SYMBOL_RX_NO_ERROR 0x08
|
||||
|
|
@ -55,55 +54,41 @@
|
|||
// RX_FRAMING follow same scheme than TX_FRAMING
|
||||
# define SYMBOL_RX_FRAMING 0x03
|
||||
|
||||
# define REG_CIU_TX_AUTO 0x6305
|
||||
// PN53X_REG_CIU_TxAuto
|
||||
# define SYMBOL_FORCE_100_ASK 0x40
|
||||
# define SYMBOL_AUTO_WAKE_UP 0x20
|
||||
# define SYMBOL_INITIAL_RF_ON 0x04
|
||||
|
||||
# define REG_CIU_TXSEL 0x6306
|
||||
|
||||
# define REG_CIU_MANUAL_RCV 0x630D
|
||||
// PN53X_REG_CIU_ManualRCV
|
||||
# define SYMBOL_PARITY_DISABLE 0x10
|
||||
|
||||
# define REG_CIU_TMODE 0x631A
|
||||
// PN53X_REG_CIU_TMode
|
||||
# define SYMBOL_TAUTO 0x80
|
||||
# define SYMBOL_TPRESCALERHI 0x0F
|
||||
|
||||
# define REG_CIU_TPRESCALER 0x631B
|
||||
// PN53X_REG_CIU_TPrescaler
|
||||
# define SYMBOL_TPRESCALERLO 0xFF
|
||||
|
||||
# define REG_CIU_TRELOADVALHI 0x631C
|
||||
|
||||
# define REG_CIU_TRELOADVALLO 0x631D
|
||||
|
||||
# define REG_CIU_TCOUNTERVALHI 0x631E
|
||||
|
||||
# define REG_CIU_TCOUNTERVALLO 0x631F
|
||||
|
||||
# define REG_CIU_COMMAND 0x6331
|
||||
// PN53X_REG_CIU_Command
|
||||
# define SYMBOL_COMMAND 0x0F
|
||||
# define SYMBOL_COMMAND_TRANSCEIVE 0xC
|
||||
|
||||
# define REG_CIU_STATUS2 0x6338
|
||||
// PN53X_REG_CIU_Status2
|
||||
# define SYMBOL_MF_CRYPTO1_ON 0x08
|
||||
|
||||
# define REG_CIU_FIFODATA 0x6339
|
||||
|
||||
# define REG_CIU_FIFOLEVEL 0x633A
|
||||
// PN53X_REG_CIU_FIFOLevel
|
||||
# define SYMBOL_FLUSH_BUFFER 0x80
|
||||
# define SYMBOL_FIFO_LEVEL 0x7F
|
||||
|
||||
# define REG_CIU_CONTROL 0x633C
|
||||
// PN53X_REG_CIU_Control
|
||||
# define SYMBOL_INITIATOR 0x10
|
||||
# define SYMBOL_RX_LAST_BITS 0x07
|
||||
|
||||
# define REG_CIU_BIT_FRAMING 0x633D
|
||||
// PN53X_REG_CIU_BitFraming
|
||||
# define SYMBOL_START_SEND 0x80
|
||||
# define SYMBOL_RX_ALIGN 0x70
|
||||
# define SYMBOL_TX_LAST_BITS 0x07
|
||||
|
||||
# define SFR_P3CFGB 0xFFFD
|
||||
# define SFR_P3 0xFFB0
|
||||
// PN53X Support Byte flags
|
||||
#define SUPPORT_ISO14443A 0x01
|
||||
#define SUPPORT_ISO14443B 0x02
|
||||
|
|
@ -153,7 +138,7 @@ struct pn53x_io {
|
|||
|
||||
/* defines */
|
||||
#define PN53X_CACHE_REGISTER_MIN_ADDRESS PN53X_REG_CIU_Mode
|
||||
#define PN53X_CACHE_REGISTER_MAX_ADDRESS PN53X_REG_CIUColl
|
||||
#define PN53X_CACHE_REGISTER_MAX_ADDRESS PN53X_REG_CIU_Coll
|
||||
#define PN53X_CACHE_REGISTER_SIZE ((PN53X_CACHE_REGISTER_MAX_ADDRESS - PN53X_CACHE_REGISTER_MIN_ADDRESS) + 1)
|
||||
struct pn53x_data {
|
||||
/** Chip type (PN531, PN532 or PN533)*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue