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chips/pn53x: remove double defines for pn53x registers.

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This commit is contained in:
Romuald Conty 2011-05-10 15:13:19 +00:00
parent e4dfa75045
commit d37b917352
5 changed files with 74 additions and 88 deletions
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21
libnfc/chips/pn53x-internal.h
View file

@ -226,6 +226,7 @@ typedef struct {
#endif #endif
// Register addresses // Register addresses
#define PN53X_REG_Control_switch_rng 0x6106
#define PN53X_REG_CIU_Mode 0x6301 #define PN53X_REG_CIU_Mode 0x6301
#define PN53X_REG_CIU_TxMode 0x6302 #define PN53X_REG_CIU_TxMode 0x6302
#define PN53X_REG_CIU_RxMode 0x6303 #define PN53X_REG_CIU_RxMode 0x6303
@ -283,11 +284,11 @@ typedef struct {
#define PN53X_REG_CIU_Status1 0x6337 #define PN53X_REG_CIU_Status1 0x6337
#define PN53X_REG_CIU_Status2 0x6338 #define PN53X_REG_CIU_Status2 0x6338
#define PN53X_REG_CIU_FIFOData 0x6339 #define PN53X_REG_CIU_FIFOData 0x6339
#define PN53X_REG_CIUFIFOLevel 0x633A #define PN53X_REG_CIU_FIFOLevel 0x633A
#define PN53X_REG_CIUWaterLevel 0x633B #define PN53X_REG_CIU_WaterLevel 0x633B
#define PN53X_REG_CIUControl 0x633C #define PN53X_REG_CIU_Control 0x633C
#define PN53X_REG_CIUBitFraming 0x633D #define PN53X_REG_CIU_BitFraming 0x633D
#define PN53X_REG_CIUColl 0x633E #define PN53X_REG_CIU_Coll 0x633E
#define PN53X_SFR_P3 0xFFB0 #define PN53X_SFR_P3 0xFFB0
@ -358,11 +359,11 @@ static const pn53x_register pn53x_registers[] = {
PNREG (PN53X_REG_CIU_Status1, "Contains status flags of the CRC, Interrupt Request System and FIFO buffer"), PNREG (PN53X_REG_CIU_Status1, "Contains status flags of the CRC, Interrupt Request System and FIFO buffer"),
PNREG (PN53X_REG_CIU_Status2, "Contain status flags of the receiver, transmitter and Data Mode Detector"), PNREG (PN53X_REG_CIU_Status2, "Contain status flags of the receiver, transmitter and Data Mode Detector"),
PNREG (PN53X_REG_CIU_FIFOData, "In- and output of 64 byte FIFO buffer"), PNREG (PN53X_REG_CIU_FIFOData, "In- and output of 64 byte FIFO buffer"),
PNREG (PN53X_REG_CIUFIFOLevel, "Indicates the number of bytes stored in the FIFO"), PNREG (PN53X_REG_CIU_FIFOLevel, "Indicates the number of bytes stored in the FIFO"),
PNREG (PN53X_REG_CIUWaterLevel, "Defines the thresholds for FIFO under- and overflow warning"), PNREG (PN53X_REG_CIU_WaterLevel, "Defines the thresholds for FIFO under- and overflow warning"),
PNREG (PN53X_REG_CIUControl, "Contains miscellaneous control bits"), PNREG (PN53X_REG_CIU_Control, "Contains miscellaneous control bits"),
PNREG (PN53X_REG_CIUBitFraming, "Adjustments for bit oriented frames"), PNREG (PN53X_REG_CIU_BitFraming, "Adjustments for bit oriented frames"),
PNREG (PN53X_REG_CIUColl, "Defines the first bit collision detected on the RF interface"), PNREG (PN53X_REG_CIU_Coll, "Defines the first bit collision detected on the RF interface"),
// SFR // SFR
PNREG (PN53X_SFR_P3CFGA, "Port 3 configuration"), PNREG (PN53X_SFR_P3CFGA, "Port 3 configuration"),

78
libnfc/chips/pn53x.c
View file

@ -95,7 +95,7 @@ pn53x_reset_settings(nfc_device_t * pnd)
{ {
// Reset the ending transmission bits register, it is unknown what the last tranmission used there // Reset the ending transmission bits register, it is unknown what the last tranmission used there
CHIP_DATA (pnd)->ui8TxBits = 0; CHIP_DATA (pnd)->ui8TxBits = 0;
if (!pn53x_write_register (pnd, REG_CIU_BIT_FRAMING, SYMBOL_TX_LAST_BITS, 0x00)) { if (!pn53x_write_register (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_TX_LAST_BITS, 0x00)) {
return false; return false;
} }
return true; return true;
@ -193,7 +193,7 @@ pn53x_set_tx_bits (nfc_device_t * pnd, const uint8_t ui8Bits)
// Test if we need to update the transmission bits register setting // Test if we need to update the transmission bits register setting
if (CHIP_DATA (pnd)->ui8TxBits != ui8Bits) { if (CHIP_DATA (pnd)->ui8TxBits != ui8Bits) {
// Set the amount of transmission bits in the PN53X chip register // Set the amount of transmission bits in the PN53X chip register
if (!pn53x_write_register (pnd, REG_CIU_BIT_FRAMING, SYMBOL_TX_LAST_BITS, ui8Bits)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_TX_LAST_BITS, ui8Bits))
return false; return false;
// Store the new setting // Store the new setting
@ -626,9 +626,9 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
// Enable or disable automatic receiving/sending of CRC bytes // Enable or disable automatic receiving/sending of CRC bytes
// TX and RX are both represented by the symbol 0x80 // TX and RX are both represented by the symbol 0x80
btValue = (bEnable) ? 0x80 : 0x00; btValue = (bEnable) ? 0x80 : 0x00;
if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_CRC_ENABLE, btValue)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_CRC_ENABLE, btValue))
return false; return false;
if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_CRC_ENABLE, btValue)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_CRC_ENABLE, btValue))
return false; return false;
pnd->bCrc = bEnable; pnd->bCrc = bEnable;
break; break;
@ -636,7 +636,7 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
case NDO_HANDLE_PARITY: case NDO_HANDLE_PARITY:
// Handle parity bit by PN53X chip or parse it as data bit // Handle parity bit by PN53X chip or parse it as data bit
btValue = (bEnable) ? 0x00 : SYMBOL_PARITY_DISABLE; btValue = (bEnable) ? 0x00 : SYMBOL_PARITY_DISABLE;
if (!pn53x_write_register (pnd, REG_CIU_MANUAL_RCV, SYMBOL_PARITY_DISABLE, btValue)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_ManualRCV, SYMBOL_PARITY_DISABLE, btValue))
return false; return false;
pnd->bPar = bEnable; pnd->bPar = bEnable;
break; break;
@ -655,7 +655,7 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
case NDO_ACTIVATE_CRYPTO1: case NDO_ACTIVATE_CRYPTO1:
btValue = (bEnable) ? SYMBOL_MF_CRYPTO1_ON : 0x00; btValue = (bEnable) ? SYMBOL_MF_CRYPTO1_ON : 0x00;
if (!pn53x_write_register (pnd, REG_CIU_STATUS2, SYMBOL_MF_CRYPTO1_ON, btValue)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_Status2, SYMBOL_MF_CRYPTO1_ON, btValue))
return false; return false;
break; break;
@ -679,13 +679,13 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
case NDO_ACCEPT_INVALID_FRAMES: case NDO_ACCEPT_INVALID_FRAMES:
btValue = (bEnable) ? SYMBOL_RX_NO_ERROR : 0x00; btValue = (bEnable) ? SYMBOL_RX_NO_ERROR : 0x00;
if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_NO_ERROR, btValue)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_NO_ERROR, btValue))
return false; return false;
break; break;
case NDO_ACCEPT_MULTIPLE_FRAMES: case NDO_ACCEPT_MULTIPLE_FRAMES:
btValue = (bEnable) ? SYMBOL_RX_MULTIPLE : 0x00; btValue = (bEnable) ? SYMBOL_RX_MULTIPLE : 0x00;
if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_MULTIPLE, btValue)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_MULTIPLE, btValue))
return false; return false;
return true; return true;
break; break;
@ -702,14 +702,14 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
return true; return true;
} }
// Force pn53x to be in ISO14443-A mode // Force pn53x to be in ISO14443-A mode
if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_FRAMING, 0x00)) { if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_FRAMING, 0x00)) {
return false; return false;
} }
if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_FRAMING, 0x00)) { if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_FRAMING, 0x00)) {
return false; return false;
} }
// Set the PN53X to force 100% ASK Modified miller decoding (default for 14443A cards) // Set the PN53X to force 100% ASK Modified miller decoding (default for 14443A cards)
if (!pn53x_write_register (pnd, REG_CIU_TX_AUTO, SYMBOL_FORCE_100_ASK, 0x40)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxAuto, SYMBOL_FORCE_100_ASK, 0x40))
return false; return false;
return true; return true;
@ -721,10 +721,10 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
return true; return true;
} }
// Force pn53x to be in ISO14443-B mode // Force pn53x to be in ISO14443-B mode
if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_FRAMING, 0x03)) { if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_FRAMING, 0x03)) {
return false; return false;
} }
if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_FRAMING, 0x03)) { if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_FRAMING, 0x03)) {
return false; return false;
} }
@ -737,10 +737,10 @@ pn53x_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bool b
return true; return true;
} }
// Force pn53x to be at 106 kbps // Force pn53x to be at 106 kbps
if (!pn53x_write_register (pnd, REG_CIU_TX_MODE, SYMBOL_TX_SPEED, 0x00)) { if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxMode, SYMBOL_TX_SPEED, 0x00)) {
return false; return false;
} }
if (!pn53x_write_register (pnd, REG_CIU_RX_MODE, SYMBOL_RX_SPEED, 0x00)) { if (!pn53x_write_register (pnd, PN53X_REG_CIU_RxMode, SYMBOL_RX_SPEED, 0x00)) {
return false; return false;
} }
@ -820,7 +820,7 @@ pn53x_initiator_init (nfc_device_t * pnd)
pn53x_reset_settings(pnd); pn53x_reset_settings(pnd);
// Configure the PN53X to be an Initiator or Reader/Writer // Configure the PN53X to be an Initiator or Reader/Writer
if (!pn53x_write_register (pnd, REG_CIU_CONTROL, SYMBOL_INITIATOR, 0x10)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_Control, SYMBOL_INITIATOR, 0x10))
return false; return false;
CHIP_DATA (pnd)->operating_mode = INITIATOR; CHIP_DATA (pnd)->operating_mode = INITIATOR;
@ -1006,7 +1006,7 @@ pn53x_initiator_transceive_bits (nfc_device_t * pnd, const byte_t * pbtTx, const
return false; return false;
// Get the last bit-count that is stored in the received byte // Get the last bit-count that is stored in the received byte
if (!pn53x_read_register (pnd, REG_CIU_CONTROL, &ui8rcc)) if (!pn53x_read_register (pnd, PN53X_REG_CIU_Control, &ui8rcc))
return false; return false;
ui8Bits = ui8rcc & SYMBOL_RX_LAST_BITS; ui8Bits = ui8rcc & SYMBOL_RX_LAST_BITS;
@ -1082,10 +1082,10 @@ void __pn53x_init_timer(nfc_device_t * pnd)
uint16_t prescaler = 0; uint16_t prescaler = 0;
uint16_t reloadval = 0xFFFF; uint16_t reloadval = 0xFFFF;
// Initialize timer // Initialize timer
pn53x_write_register (pnd, REG_CIU_TMODE, 0xFF, SYMBOL_TAUTO | ((prescaler >> 8) & SYMBOL_TPRESCALERHI)); pn53x_write_register (pnd, PN53X_REG_CIU_TMode, 0xFF, SYMBOL_TAUTO | ((prescaler >> 8) & SYMBOL_TPRESCALERHI));
pn53x_write_register (pnd, REG_CIU_TPRESCALER, 0xFF, (prescaler & SYMBOL_TPRESCALERLO)); pn53x_write_register (pnd, PN53X_REG_CIU_TPrescaler, 0xFF, (prescaler & SYMBOL_TPRESCALERLO));
pn53x_write_register (pnd, REG_CIU_TRELOADVALHI, 0xFF, (reloadval >> 8) & 0xFF); pn53x_write_register (pnd, PN53X_REG_CIU_TReloadVal_hi, 0xFF, (reloadval >> 8) & 0xFF);
pn53x_write_register (pnd, REG_CIU_TRELOADVALLO, 0xFF, reloadval & 0xFF); pn53x_write_register (pnd, PN53X_REG_CIU_TReloadVal_lo, 0xFF, reloadval & 0xFF);
} }
uint16_t __pn53x_get_timer(nfc_device_t * pnd, const uint8_t last_cmd_byte) uint16_t __pn53x_get_timer(nfc_device_t * pnd, const uint8_t last_cmd_byte)
@ -1094,8 +1094,8 @@ uint16_t __pn53x_get_timer(nfc_device_t * pnd, const uint8_t last_cmd_byte)
uint8_t counter_hi, counter_lo; uint8_t counter_hi, counter_lo;
uint16_t counter, cycles; uint16_t counter, cycles;
// Read timer // Read timer
pn53x_read_register (pnd, REG_CIU_TCOUNTERVALHI, &counter_hi); pn53x_read_register (pnd, PN53X_REG_CIU_TCounterVal_hi, &counter_hi);
pn53x_read_register (pnd, REG_CIU_TCOUNTERVALLO, &counter_lo); pn53x_read_register (pnd, PN53X_REG_CIU_TCounterVal_lo, &counter_lo);
counter = counter_hi; counter = counter_hi;
counter = (counter << 8) + counter_lo; counter = (counter << 8) + counter_lo;
if (counter == 0) { if (counter == 0) {
@ -1160,14 +1160,14 @@ pn53x_initiator_transceive_bits_timed (nfc_device_t * pnd, const byte_t * pbtTx,
// E.g. on SCL3711 timer settings are reset by 0x42 InCommunicateThru command to: // E.g. on SCL3711 timer settings are reset by 0x42 InCommunicateThru command to:
// 631a=82 631b=a5 631c=02 631d=00 // 631a=82 631b=a5 631c=02 631d=00
// Prepare FIFO // Prepare FIFO
pn53x_WriteRegister (pnd, REG_CIU_COMMAND, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE); pn53x_WriteRegister (pnd, PN53X_REG_CIU_Command, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE);
pn53x_WriteRegister (pnd, REG_CIU_FIFOLEVEL, SYMBOL_FLUSH_BUFFER); pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOLevel, SYMBOL_FLUSH_BUFFER);
for (i=0; i< ((szTxBits / 8) + 1); i++) { for (i=0; i< ((szTxBits / 8) + 1); i++) {
pn53x_WriteRegister (pnd, REG_CIU_FIFODATA, pbtTx[i]); pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOData, pbtTx[i]);
} }
// Send data // Send data
pn53x_WriteRegister (pnd, REG_CIU_BIT_FRAMING, SYMBOL_START_SEND | ((szTxBits % 8) & SYMBOL_TX_LAST_BITS)); pn53x_WriteRegister (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_START_SEND | ((szTxBits % 8) & SYMBOL_TX_LAST_BITS));
// Recv data // Recv data
*pszRxBits = 0; *pszRxBits = 0;
@ -1176,16 +1176,16 @@ pn53x_initiator_transceive_bits_timed (nfc_device_t * pnd, const byte_t * pbtTx,
// responses coming very late anyway. // responses coming very late anyway.
// Ideally we should implement a real timer here too but looping a few times is good enough. // Ideally we should implement a real timer here too but looping a few times is good enough.
for (i=0; i<4; i++) { for (i=0; i<4; i++) {
pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz); pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
if (sz > 0) if (sz > 0)
break; break;
} }
while (1) { while (1) {
for (i=0; i<sz; i++) { for (i=0; i<sz; i++) {
pn53x_read_register (pnd, REG_CIU_FIFODATA, &(pbtRx[i+*pszRxBits])); pn53x_read_register (pnd, PN53X_REG_CIU_FIFOData, &(pbtRx[i+*pszRxBits]));
} }
*pszRxBits += (size_t) (sz & SYMBOL_FIFO_LEVEL); *pszRxBits += (size_t) (sz & SYMBOL_FIFO_LEVEL);
pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz); pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
if (sz == 0) if (sz == 0)
break; break;
} }
@ -1222,14 +1222,14 @@ pn53x_initiator_transceive_bytes_timed (nfc_device_t * pnd, const byte_t * pbtTx
// E.g. on SCL3711 timer settings are reset by 0x42 InCommunicateThru command to: // E.g. on SCL3711 timer settings are reset by 0x42 InCommunicateThru command to:
// 631a=82 631b=a5 631c=02 631d=00 // 631a=82 631b=a5 631c=02 631d=00
// Prepare FIFO // Prepare FIFO
pn53x_WriteRegister (pnd, REG_CIU_COMMAND, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE); pn53x_WriteRegister (pnd, PN53X_REG_CIU_Command, SYMBOL_COMMAND & SYMBOL_COMMAND_TRANSCEIVE);
pn53x_WriteRegister (pnd, REG_CIU_FIFOLEVEL, SYMBOL_FLUSH_BUFFER); pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOLevel, SYMBOL_FLUSH_BUFFER);
for (i=0; i< szTx; i++) { for (i=0; i< szTx; i++) {
pn53x_WriteRegister (pnd, REG_CIU_FIFODATA, pbtTx[i]); pn53x_WriteRegister (pnd, PN53X_REG_CIU_FIFOData, pbtTx[i]);
} }
// Send data // Send data
pn53x_WriteRegister (pnd, REG_CIU_BIT_FRAMING, SYMBOL_START_SEND); pn53x_WriteRegister (pnd, PN53X_REG_CIU_BitFraming, SYMBOL_START_SEND);
// Recv data // Recv data
*pszRx = 0; *pszRx = 0;
@ -1238,16 +1238,16 @@ pn53x_initiator_transceive_bytes_timed (nfc_device_t * pnd, const byte_t * pbtTx
// responses coming very late anyway. // responses coming very late anyway.
// Ideally we should implement a real timer here too but looping a few times is good enough. // Ideally we should implement a real timer here too but looping a few times is good enough.
for (i=0; i<4; i++) { for (i=0; i<4; i++) {
pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz); pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
if (sz > 0) if (sz > 0)
break; break;
} }
while (1) { while (1) {
for (i=0; i<sz; i++) { for (i=0; i<sz; i++) {
pn53x_read_register (pnd, REG_CIU_FIFODATA, &(pbtRx[i+*pszRx])); pn53x_read_register (pnd, PN53X_REG_CIU_FIFOData, &(pbtRx[i+*pszRx]));
} }
*pszRx += (size_t) (sz & SYMBOL_FIFO_LEVEL); *pszRx += (size_t) (sz & SYMBOL_FIFO_LEVEL);
pn53x_read_register (pnd, REG_CIU_FIFOLEVEL, &sz); pn53x_read_register (pnd, PN53X_REG_CIU_FIFOLevel, &sz);
if (sz == 0) if (sz == 0)
break; break;
} }
@ -1323,7 +1323,7 @@ pn53x_target_init (nfc_device_t * pnd, nfc_target_t * pnt, byte_t * pbtRx, size_
} }
// Let the PN53X be activated by the RF level detector from power down mode // Let the PN53X be activated by the RF level detector from power down mode
if (!pn53x_write_register (pnd, REG_CIU_TX_AUTO, SYMBOL_INITIAL_RF_ON, 0x04)) if (!pn53x_write_register (pnd, PN53X_REG_CIU_TxAuto, SYMBOL_INITIAL_RF_ON, 0x04))
return false; return false;
byte_t abtMifareParams[6]; byte_t abtMifareParams[6];
@ -1503,7 +1503,7 @@ pn53x_target_receive_bits (nfc_device_t * pnd, byte_t * pbtRx, size_t * pszRxBit
// Get the last bit-count that is stored in the received byte // Get the last bit-count that is stored in the received byte
uint8_t ui8rcc; uint8_t ui8rcc;
if (!pn53x_read_register (pnd, REG_CIU_CONTROL, &ui8rcc)) if (!pn53x_read_register (pnd, PN53X_REG_CIU_Control, &ui8rcc))
return false; return false;
uint8_t ui8Bits = ui8rcc & SYMBOL_RX_LAST_BITS; uint8_t ui8Bits = ui8rcc & SYMBOL_RX_LAST_BITS;

41
libnfc/chips/pn53x.h
View file

@ -30,9 +30,8 @@
# include <nfc/nfc-types.h> # include <nfc/nfc-types.h>
# include "pn53x-internal.h" # include "pn53x-internal.h"
// TODO Remove double register address defines
// Registers and symbols masks used to covers parts within a register // Registers and symbols masks used to covers parts within a register
# define REG_CIU_TX_MODE 0x6302 // PN53X_REG_CIU_TxMode
# define SYMBOL_TX_CRC_ENABLE 0x80 # define SYMBOL_TX_CRC_ENABLE 0x80
# define SYMBOL_TX_SPEED 0x70 # define SYMBOL_TX_SPEED 0x70
// TX_FRAMING bits explanation: // TX_FRAMING bits explanation:
@ -42,12 +41,12 @@
// 11 : ISO/IEC 14443B // 11 : ISO/IEC 14443B
# define SYMBOL_TX_FRAMING 0x03 # define SYMBOL_TX_FRAMING 0x03
# define REG_CONTROL_SWITCH_RNG 0x6106 // PN53X_REG_Control_switch_rng
# define SYMBOL_CURLIMOFF 0x08 /* When set to 1, the 100 mA current limitations is desactivated. */ # define SYMBOL_CURLIMOFF 0x08 /* When set to 1, the 100 mA current limitations is desactivated. */
# define SYMBOL_SIC_SWITCH_EN 0x10 /* When set to logic 1, the SVDD switch is enabled and the SVDD output delivers power to secure IC and internal pads (SIGIN, SIGOUT and P34). */ # define SYMBOL_SIC_SWITCH_EN 0x10 /* When set to logic 1, the SVDD switch is enabled and the SVDD output delivers power to secure IC and internal pads (SIGIN, SIGOUT and P34). */
# define SYMBOL_RANDOM_DATAREADY 0x02 /* When set to logic 1, a new random number is available. */ # define SYMBOL_RANDOM_DATAREADY 0x02 /* When set to logic 1, a new random number is available. */
# define REG_CIU_RX_MODE 0x6303 // PN53X_REG_CIU_RxMode
# define SYMBOL_RX_CRC_ENABLE 0x80 # define SYMBOL_RX_CRC_ENABLE 0x80
# define SYMBOL_RX_SPEED 0x70 # define SYMBOL_RX_SPEED 0x70
# define SYMBOL_RX_NO_ERROR 0x08 # define SYMBOL_RX_NO_ERROR 0x08
@ -55,55 +54,41 @@
// RX_FRAMING follow same scheme than TX_FRAMING // RX_FRAMING follow same scheme than TX_FRAMING
# define SYMBOL_RX_FRAMING 0x03 # define SYMBOL_RX_FRAMING 0x03
# define REG_CIU_TX_AUTO 0x6305 // PN53X_REG_CIU_TxAuto
# define SYMBOL_FORCE_100_ASK 0x40 # define SYMBOL_FORCE_100_ASK 0x40
# define SYMBOL_AUTO_WAKE_UP 0x20 # define SYMBOL_AUTO_WAKE_UP 0x20
# define SYMBOL_INITIAL_RF_ON 0x04 # define SYMBOL_INITIAL_RF_ON 0x04
# define REG_CIU_TXSEL 0x6306 // PN53X_REG_CIU_ManualRCV
# define REG_CIU_MANUAL_RCV 0x630D
# define SYMBOL_PARITY_DISABLE 0x10 # define SYMBOL_PARITY_DISABLE 0x10
# define REG_CIU_TMODE 0x631A // PN53X_REG_CIU_TMode
# define SYMBOL_TAUTO 0x80 # define SYMBOL_TAUTO 0x80
# define SYMBOL_TPRESCALERHI 0x0F # define SYMBOL_TPRESCALERHI 0x0F
# define REG_CIU_TPRESCALER 0x631B // PN53X_REG_CIU_TPrescaler
# define SYMBOL_TPRESCALERLO 0xFF # define SYMBOL_TPRESCALERLO 0xFF
# define REG_CIU_TRELOADVALHI 0x631C // PN53X_REG_CIU_Command
# define REG_CIU_TRELOADVALLO 0x631D
# define REG_CIU_TCOUNTERVALHI 0x631E
# define REG_CIU_TCOUNTERVALLO 0x631F
# define REG_CIU_COMMAND 0x6331
# define SYMBOL_COMMAND 0x0F # define SYMBOL_COMMAND 0x0F
# define SYMBOL_COMMAND_TRANSCEIVE 0xC # define SYMBOL_COMMAND_TRANSCEIVE 0xC
# define REG_CIU_STATUS2 0x6338 // PN53X_REG_CIU_Status2
# define SYMBOL_MF_CRYPTO1_ON 0x08 # define SYMBOL_MF_CRYPTO1_ON 0x08
# define REG_CIU_FIFODATA 0x6339 // PN53X_REG_CIU_FIFOLevel
# define REG_CIU_FIFOLEVEL 0x633A
# define SYMBOL_FLUSH_BUFFER 0x80 # define SYMBOL_FLUSH_BUFFER 0x80
# define SYMBOL_FIFO_LEVEL 0x7F # define SYMBOL_FIFO_LEVEL 0x7F
# define REG_CIU_CONTROL 0x633C // PN53X_REG_CIU_Control
# define SYMBOL_INITIATOR 0x10 # define SYMBOL_INITIATOR 0x10
# define SYMBOL_RX_LAST_BITS 0x07 # define SYMBOL_RX_LAST_BITS 0x07
# define REG_CIU_BIT_FRAMING 0x633D // PN53X_REG_CIU_BitFraming
# define SYMBOL_START_SEND 0x80 # define SYMBOL_START_SEND 0x80
# define SYMBOL_RX_ALIGN 0x70 # define SYMBOL_RX_ALIGN 0x70
# define SYMBOL_TX_LAST_BITS 0x07 # define SYMBOL_TX_LAST_BITS 0x07
# define SFR_P3CFGB 0xFFFD
# define SFR_P3 0xFFB0
// PN53X Support Byte flags // PN53X Support Byte flags
#define SUPPORT_ISO14443A 0x01 #define SUPPORT_ISO14443A 0x01
#define SUPPORT_ISO14443B 0x02 #define SUPPORT_ISO14443B 0x02
@ -153,7 +138,7 @@ struct pn53x_io {
/* defines */ /* defines */
#define PN53X_CACHE_REGISTER_MIN_ADDRESS PN53X_REG_CIU_Mode #define PN53X_CACHE_REGISTER_MIN_ADDRESS PN53X_REG_CIU_Mode
#define PN53X_CACHE_REGISTER_MAX_ADDRESS PN53X_REG_CIUColl #define PN53X_CACHE_REGISTER_MAX_ADDRESS PN53X_REG_CIU_Coll
#define PN53X_CACHE_REGISTER_SIZE ((PN53X_CACHE_REGISTER_MAX_ADDRESS - PN53X_CACHE_REGISTER_MIN_ADDRESS) + 1) #define PN53X_CACHE_REGISTER_SIZE ((PN53X_CACHE_REGISTER_MAX_ADDRESS - PN53X_CACHE_REGISTER_MIN_ADDRESS) + 1)
struct pn53x_data { struct pn53x_data {
/** Chip type (PN531, PN532 or PN533)*/ /** Chip type (PN531, PN532 or PN533)*/

14
libnfc/drivers/pn53x_usb.c
View file

@ -347,7 +347,7 @@ pn53x_usb_disconnect (nfc_device_t * pnd)
if (DRIVER_DATA (pnd)->model == ASK_LOGO) { if (DRIVER_DATA (pnd)->model == ASK_LOGO) {
/* Set P30, P31, P32, P33, P35 to logic 1 and P34 to 0 logic */ /* Set P30, P31, P32, P33, P35 to logic 1 and P34 to 0 logic */
/* ie. Switch all LEDs off and turn off progressive field */ /* ie. Switch all LEDs off and turn off progressive field */
pn53x_write_register (pnd, SFR_P3, 0xFF, _BV (P30) | _BV (P31) | _BV (P32) | _BV (P33) | _BV (P35)); pn53x_write_register (pnd, PN53X_SFR_P3, 0xFF, _BV (P30) | _BV (P31) | _BV (P32) | _BV (P33) | _BV (P35));
} }
int res; int res;
@ -553,13 +553,13 @@ pn53x_usb_init (nfc_device_t *pnd)
DBG ("ASK LoGO initialization."); DBG ("ASK LoGO initialization.");
/* Internal registers */ /* Internal registers */
/* Disable 100mA current limit, Power on Secure IC (SVDD) */ /* Disable 100mA current limit, Power on Secure IC (SVDD) */
pn53x_write_register (pnd, REG_CONTROL_SWITCH_RNG, 0xFF, SYMBOL_CURLIMOFF | SYMBOL_SIC_SWITCH_EN | SYMBOL_RANDOM_DATAREADY); pn53x_write_register (pnd, PN53X_REG_Control_switch_rng, 0xFF, SYMBOL_CURLIMOFF | SYMBOL_SIC_SWITCH_EN | SYMBOL_RANDOM_DATAREADY);
/* Select the signal to be output on SIGOUT: Modulation signal (envelope) from the internal coder */ /* Select the signal to be output on SIGOUT: Modulation signal (envelope) from the internal coder */
pn53x_write_register (pnd, REG_CIU_TXSEL, 0xFF, 0x14); pn53x_write_register (pnd, PN53X_REG_CIU_TxSel, 0xFF, 0x14);
/* SFR Registers */ /* SFR Registers */
/* Setup push-pulls for pins from P30 to P35 */ /* Setup push-pulls for pins from P30 to P35 */
pn53x_write_register (pnd, SFR_P3CFGB, 0xFF, 0x37); pn53x_write_register (pnd, PN53X_SFR_P3CFGB, 0xFF, 0x37);
/* /*
On ASK LoGO hardware: On ASK LoGO hardware:
@ -581,7 +581,7 @@ On ASK LoGO hardware:
/* Set P30, P31, P33, P35 to logic 1 and P32, P34 to 0 logic */ /* Set P30, P31, P33, P35 to logic 1 and P32, P34 to 0 logic */
/* ie. Switch LED1 on and turn off progressive field */ /* ie. Switch LED1 on and turn off progressive field */
pn53x_write_register (pnd, SFR_P3, 0xFF, _BV (P30) | _BV (P31) | _BV (P33) | _BV (P35)); pn53x_write_register (pnd, PN53X_SFR_P3, 0xFF, _BV (P30) | _BV (P31) | _BV (P33) | _BV (P35));
} }
return true; return true;
@ -598,14 +598,14 @@ pn53x_usb_configure (nfc_device_t * pnd, const nfc_device_option_t ndo, const bo
if (NDO_ACTIVATE_FIELD == ndo) { if (NDO_ACTIVATE_FIELD == ndo) {
/* Switch on/off LED2 and Progressive Field GPIO according to ACTIVATE_FIELD option */ /* Switch on/off LED2 and Progressive Field GPIO according to ACTIVATE_FIELD option */
DBG ("Switch progressive field %s", bEnable ? "On" : "Off"); DBG ("Switch progressive field %s", bEnable ? "On" : "Off");
if (!pn53x_write_register (pnd, SFR_P3, _BV(P31) | _BV(P34), bEnable ? _BV (P34) : _BV (P31))) if (!pn53x_write_register (pnd, PN53X_SFR_P3, _BV(P31) | _BV(P34), bEnable ? _BV (P34) : _BV (P31)))
return false; return false;
} }
break; break;
case SCM_SCL3711: case SCM_SCL3711:
if (NDO_ACTIVATE_FIELD == ndo) { if (NDO_ACTIVATE_FIELD == ndo) {
// Switch on/off LED according to ACTIVATE_FIELD option // Switch on/off LED according to ACTIVATE_FIELD option
if (!pn53x_write_register (pnd, SFR_P3, _BV (P32), bEnable ? 0 : _BV (P32))) if (!pn53x_write_register (pnd, PN53X_SFR_P3, _BV (P32), bEnable ? 0 : _BV (P32)))
return false; return false;
} }
break; break;

8
test/test_register_access.c
View file

@ -25,20 +25,20 @@ test_register_endianness (void)
uint8_t value; uint8_t value;
/* Set a 0xAA test value in writable register memory to test register access */ /* Set a 0xAA test value in writable register memory to test register access */
res = pn53x_write_register (device, REG_CIU_TX_MODE, 0xFF, 0xAA); res = pn53x_write_register (device, PN53X_REG_CIU_TxMode, 0xFF, 0xAA);
cut_assert_true (res, cut_message ("write register value to 0xAA")); cut_assert_true (res, cut_message ("write register value to 0xAA"));
/* Get test value from register memory */ /* Get test value from register memory */
res = pn53x_read_register (device, REG_CIU_TX_MODE, &value); res = pn53x_read_register (device, PN53X_REG_CIU_TxMode, &value);
cut_assert_true (res, cut_message ("read register value")); cut_assert_true (res, cut_message ("read register value"));
cut_assert_equal_uint (0xAA, value, cut_message ("check register value")); cut_assert_equal_uint (0xAA, value, cut_message ("check register value"));
/* Set a 0x55 test value in writable register memory to test register access */ /* Set a 0x55 test value in writable register memory to test register access */
res = pn53x_write_register (device, REG_CIU_TX_MODE, 0xFF, 0x55); res = pn53x_write_register (device, PN53X_REG_CIU_TxMode, 0xFF, 0x55);
cut_assert_true (res, cut_message ("write register value to 0x55")); cut_assert_true (res, cut_message ("write register value to 0x55"));
/* Get test value from register memory */ /* Get test value from register memory */
res = pn53x_read_register (device, REG_CIU_TX_MODE, &value); res = pn53x_read_register (device, PN53X_REG_CIU_TxMode, &value);
cut_assert_true (res, cut_message ("read register value")); cut_assert_true (res, cut_message ("read register value"));
cut_assert_equal_uint (0x55, value, cut_message ("check register value")); cut_assert_equal_uint (0x55, value, cut_message ("check register value"));